Distributed switch memory architecture

Abstract

A distributed memory switch system for transmitting packets from source ports to destination ports, comprising: a plurality of ports including a source port and a destination port wherein a packet is transmitted from the source port to the destination port; a memory pool; and an interconnection stage coupled between the plurality of ports and the memory pool such that the interconnection stage permits a packet to be transmitted from the source port to the destination port via the memory pool.

1. A distributed memory switch system, comprising:
 a plurality of ports including a source port and a destination port; 
 a memory pool; 
 an interconnection stage to couple between the plurality of ports and the memory pool such that the interconnection stage permits a packet to be sent from the source port to the destination port via the memory pool, the interconnection stage to split the packet received from the source port into multiple packet portions for storage in the memory pool, wherein the interconnection stage includes a switch stage to couple to the plurality of ports, and a memory switch to couple to the switch stage and to the memory pool; and 
 a processor to couple to the interconnection stage, the processor to assign memory space from the memory pool to the ports, and wherein the processor assigns a larger amount of memory space from the memory pool to higher speed ports and a smaller amount of memory space from the memory pool to lower speed ports. 
 
     
     
       2. The distributed memory switch system of  claim 1  wherein the processor assigns varying amounts of memory space from the memory pool to different ports. 
     
     
       3. The distributed memory switch system of  claim 1  wherein the processor assigns a same amount of memory space from the memory pool to multiple ports. 
     
     
       4. The distributed memory switch system of  claim 1  wherein the processor assigns memory space from the memory pool to the ports based upon a number of packets communicated by each port. 
     
     
       5. The distributed memory switch system of  claim 1  wherein the interconnection stage splits the packet received from the source port into multiple equal-sized packet portions for storage in the memory pool. 
     
     
       6. The distributed memory switch system of  claim 1  wherein the interconnection stage splits the packet received from the source port into at least one odd-sized packet portion for storage in the memory pool. 
     
     
       7. The distributed memory switch system of  claim 1  wherein the interconnection stage splits a first portion of the packet received from the source port into multiple equal-sized packet portions for storage in the memory pool, and a second portion of the packet received from the source port into at least one odd-sized packet portion for storage in the memory pool. 
     
     
       8. A switch system for switching packets between ports, comprising:
 an interconnection stage arranged to transmit the packets between the ports; 
 a memory pool to connect to the interconnection stage to store the packets which are received from the ports, wherein the interconnection stage splits certain of the packets received from the ports into multiple packet portions for storage in the memory pool, and the interconnection stage includes a switch stage to connect to the ports and a memory switch to connect to the switch stage and the memory pool; and 
 a processor to connect to the interconnection stage, the processor to assign memory space from the memory pool to the ports, and wherein the processor assigns a larger amount of memory space from the memory pool to higher speed ports and a smaller amount of memory space from the memory pool to lower speed ports. 
 
     
     
       9. The switch system of  claim 8  wherein the processor assigns varying amounts of memory space from the memory pool to different ports. 
     
     
       10. The switch system of  claim 8  wherein the processor assigns a same amount of memory space from the memory pool to multiple ports. 
     
     
       11. The switch system of  claim 8  wherein the processor assigns memory space from the memory pool to the ports based upon a number of packets communicated by each port. 
     
     
       12. The switch system of  claim 8  wherein the interconnection stage splits the packet received from the source port into multiple equal-sized packet portions for storage in the memory pool. 
     
     
       13. The switch system of  claim 8  wherein the interconnection stage splits the packet received from the source port into at least one odd-sized packet portion for storage in the memory pool. 
     
     
       14. The switch system of  claim 8  wherein the interconnection stage splits a first portion of the packet received from the source port into multiple equal-sized packet portions for storage in the memory pool, and a second portion of the packet received from the source port into at least one odd-sized packet portion for storage in the memory pool.