Clock generation circuit and method thereof

Abstract

The present invention generates an output clock signal CLKreq having a frequency freq between the frequency fref/A of a divided clock signal CKL 1 and the frequency fref/(A+1) of a divided clock signal CLK 2 . A clock divider circuit selectively generates divided clock signals CLK 1 , CLK 2 . A discrete value correction circuit controls the clock divider circuit so as to repeat C times the process of generating the clock signal CLK 2 once and the clock signal CLK 1 (Q−1) times and then to generate the clock signal CLK 1 R times if C<D and so as to repeat D times the process of generating the clock signal CLK 1 once and the clock signal CLK 2 (Q−1) times and then to generate the clock signal CLK 2 R times if C>D. A, B, and C are natural numbers satisfying freq=fref/(A+C/B). In D=B−C, Q is a quotient of B/C if C<D or a quotient of B/D if C>D.

1. A clock generation circuit for generating an output clock signal having a frequency freq between a frequency fref/A of a first divided clock signal and a frequency fref/(A+1) of a second divided clock signal on the basis of the first divided clock signal obtained by dividing a reference clock signal having a frequency fref by A and the second divided clock signal obtained by dividing the reference clock signal by (A+1), said clock generation circuit comprising:
 dividing means for selectively generating the first divided clock signal and the second divided clock signal and for outputting a selected divided clock signal as the output clock signal; and 
 correction means for controlling said dividing means so as: 
 if C<D, repeating C times the process of generating the second divided clock signal once and generating the first divided clock signal (Q−1) times; and 
 if C>D, repeating D times the process of generating the first divided clock signal once and generating the second divided clock signal (Q−1) times, 
 where A, B, and C are natural numbers satisfying the following formula (1):
   freq=fref/(A+C/B) (1); and 
 
 where D=B−C, Q is the quotient of B/C for C<D, and Q is the quotient of B/D for C>D. 
 
   
   
     2. The circuit according to  claim 1 , wherein said correction means further controls said dividing means so as to generate the first divided clock signal R times if C<D and controls said dividing means so as to generate the second divided clock signal R times if C>D, where R is the remainder of B/C for C<D or the remainder B/D for C>D. 
   
   
     3. The circuit according to  claim 1 , wherein said dividing means includes:
 high-pulse generation means for maintaining the first or second divided clock signal at a high level until it receives the reference clock signal n times if A=2n (n: natural number) and maintaining the first or second divided clock signal at the high level until it receives the reference clock signal (n+1) times if A=2n+1; and 
 low-pulse generation means for maintaining the first divided clock signal at a low level until it receives the reference clock signal n times and maintaining the second divided clock signal at a low level until it receives the reference clock signal (n+1) times. 
 
   
   
     4. The circuit according to  claim 1 ,
 wherein said dividing means includes:
 a high-pulse width counter for counting the reference clock signal; 
 a high-pulse width register for registering n if A=2n (n: natural number) and registering (n+1) if A=2n+1 
 a high-pulse width comparator for comparing a value of said high-pulse width counter with a value of said high-pulse width register and outputting a high-pulse width end signal if the value of said high-pulse width counter reaches the value of said high-pulse width register; 
 a low-pulse width counter for counting the reference clock signal; 
 a low-pulse width register for registering n; 
 a low-pulse width comparator for comparing a value of said low-pulse width counter with a value of said low-pulse width register and outputting a low-pulse width end signal if the value of said low-pulse width counter reaches the value of said low-pulse width register; and 
 a state control circuit for activating said high-pulse width counter in response to the low-pulse width end signal, activating said low-pulse width counter in response to said high-pulse width end signal, and selecting the first or second divided clock signal in response to a divided clock selection signal, and 
 
 wherein said correction means includes:
 a Q counter for counting the low-pulse width end signal; 
 a Q register for registering Q; 
 a Q comparator for comparing a value of the Q counter with a value of said Q register and outputting a Q end signal if the value of the Q counter reaches the value of the Q register; 
 a C/D counter for counting the Q end signal; 
 a C/D register for registering C or D; 
 a C/D comparator for comparing a value of said C/D counter with a value of said C/D register and outputting a C/D end signal if the value of the C/D counter reaches the value of said C/D register; and 
 a correction determination circuit for changing a logical level of the divided clock selection signal in response to the Q end signal and changing a logical level of the divided clock selection signal in response to the first low-pulse width end signal after receiving the Q end signal. 
 
 
   
   
     5. The circuit according to  claim 4 ,
 wherein said correction means further includes:
 an R counter for counting the low-pulse width end signal; 
 an R register for registering R; and 
 an R comparator for comparing a value of said R counter with a value of said R register and outputting an R end signal if the value of said R counter reaches the value of the R register, and 
 
 wherein said correction determination circuit activates the R register in response to the C/D end signal, 
 where R is the remainder of B/C for C<D or the remainder of B/D for C>D. 
 
   
   
     6. A clock generation method for generating an output clock signal having
 a frequency freq between a frequency fref/A of a first divided clock signal and a frequency fref/(A+1) of a second divided clock signal on the basis of the first divided clock signal obtained by dividing a reference clock signal having a frequency fref by A and the second divided clock signal obtained by dividing the reference clock signal by (A+1), said clock generation method comprising the steps of: 
 if C<D; 
 (a) generating the second divided clock signal once; 
 (b) generating the first divided clock signal (Q−1) times after generating the second divided clock signal; 
 (c) repeating the steps of (a) and (b) C times; 
 If C>D; 
 (d) generating the first divided clock signal once; 
 (e) generating the second divided clock signal (Q−1) times after generating the first divided clock signal; and 
 (f) repeating the said steps of (d) and (e) D times, 
 where A, B, and C are natural numbers satisfying the following formula (1): 
 freq=fref/(A+C/B) (1); and 
 where D=B−C, Q is the quotient of B/C for C<D, and Q is the quotient of B/D for C>D. 
 
   
   
     7. The method according to  claim 6 , further comprising the steps of:
 generating the first divided clock signal R times after said step of repeating C times if C<D; and 
 generating the second divided clock signal R times after said step of repeating D times if C>D, 
 
     where R is the remainder of B/C for C<D, or the reminder of B/D for C>D. 
   
   
     8. The method according to  claim 6 ,
 wherein said step of generating the first divided clock signal includes the steps of: 
 if A=2n (n: natural number),
 maintaining the first divided clock signal at a high level until the reference clock signal is received n times; and 
 maintaining the first divided clock signal at a low level until the reference clock signal is received n times after said step of maintaining the first divided clock signal at the high level; and 
 
 if A=2n+1,
 maintaining the first divided clock signal at the high level until the reference clock signal is received (n+1) times; and 
 maintaining the first divided clock signal at the low level until the reference clock signal is received n times after said step of maintaining the first divided clock signal at the high level, and 
 
 wherein said step of generating the second divided clock signal includes the steps of: 
 if A=2n,
 maintaining the second divided clock signal at a high level until the reference clock signal is received n times; and 
 maintaining the second divided clock signal at a low level until the reference clock signal is received (n+1) times after said step of maintaining the second divided clock signal at the high level; and 
 
 if A=2n+1,
 maintaining the second divided clock signal at the high level until the reference clock signal is received (n+1) times; and 
 
 maintaining the second divided clock signal at the low level until the reference clock signal is received (n+1) times after said step of maintaining the second divided clock signal at the high level.