Step-up voltage generator for semiconductor memory and method for controlling the same

Abstract

A step-up voltage generator for a semiconductor memory is provided which includes a level detection unit, a bank-active command generator, and an oscillation signal generator. The level detection unit compares a reference voltage with a division voltage of a pumping voltage, detects a level of the pumping voltage according to the comparison result, and generates a level detection signal. The bank-active command generator generates bank-active signals in response to a row-active command signal. The oscillation signal generator determines whether it received the bank-active signals from the bank-active command generator, replies to the bank-active signals or the level detection signal according to the determination result, and generates oscillation signals. An active-voltage UP converter performs pumping of a power-supply voltage in response to the oscillation signals, and generates a step-up voltage.

1. A step-up voltage generator for a semiconductor memory, comprising:
 a level detection unit configured to compare a reference voltage with a division voltage of a pumping voltage, detect a level of the pumping voltage according to the comparison result, and generate a level detection signal; 
 a bank-active command generator configured to generate bank-active signals in response to a row-active command signal; 
 an oscillation signal generator configured to generate pulse signals in response to the bank-active signals, and generate oscillation signals in response to the pulse signals or the level detection signal; and 
 an active-voltage UP converter configured to pump a power-supply voltage in response to the oscillation signals, and generate a step-up voltage, 
 wherein the oscillation signals are enabled when the bank-active signals are enabled or the level detection signal is enabled, 
 wherein the oscillation signal generator includes: 
 a pulse generator configured to generate pulse signals in response to the bank-active signals; 
 a first logic circuit configured to perform a NAND operation in response to the bank-active signals and the level detection signal; and 
 a second logic circuit configured to perform a NAND operation in response to output signals of the first logic circuit and the pulse generator. 
 
   
   
     2. The step-up voltage generator according to  claim 1 , wherein the first logic circuit includes at least one NAND gate, and the second logic circuit includes at least one NAND gate. 
   
   
     3. The step-up voltage generator according to  claim 1 , wherein the pulse generator includes:
 an inverter chain configured to delay the bank-active signals by a predetermined time; and 
 a third logic circuit configured to perform a NAND operation in response to an output signal of the inverter chain and the bank-active signals. 
 
   
   
     4. The step-up voltage generator according to  claim 3 , wherein the third logic circuit is composed of a NAND gate. 
   
   
     5. A step-up voltage generator for a semiconductor memory comprising:
 a bank-active input unit including pulse generators configured to generate pulse signals in response to bank-active signals; and 
 a driving-signal generator configured to determine whether the driving-signal generator received the bank-active signals from the bank-active input unit, and generate driving signals in response to the bank-active signals or a level detection signal of a pumping voltage, 
 wherein the driving signals are enabled when the bank-active signals are enabled or the level detection signal is enabled 
 wherein the driving signal generator includes: 
 a first logic circuit configured to perform a NAND operation in response to the bank-active signals and the level detection signal; and 
 a second logic circuit configured to perform a NAND operation in response to output signals of the first logic circuit and the bank-active input unit. 
 
   
   
     6. The step-up voltage generator according to  claim 5 , further comprising:
 a level detection unit configured to compare a reference voltage with a division voltage of the pumping voltage, detect a level of the pumping voltage according to the comparison result, and transmit the level detection signal to the driving-signal generator. 
 
   
   
     7. The step-up voltage generator according to  claim 5 , further comprising:
 an active-voltage UP converter configured to pump a power-supply voltage in response to the driving signals, and generate a step-up voltage. 
 
   
   
     8. The step-up voltage generator according to  claim 5 , wherein the bank-active input unit includes:
 an inverter chain configured to delay the bank-active signals by a predetermined time; and 
 a third logic circuit configured to perform a NAND operation in response to an output signal of the inverter chain and the bank-active signals. 
 
   
   
     9. A method for controlling a step-up voltage generator of a semiconductor memory, said method comprising:
 (a) receiving a level detection signal from a level detection unit for detecting a level of a pumping voltage by comparing a reference voltage with a division voltage of the pumping voltage; 
 (b) determining whether bank-active signals are received from a bank active command generator; and 
 (c) replying to the bank active signals or the level detection signal according to the determination result of (b), and generating oscillation signals; 
 (d) generating pulse signals in response to the bank-active signals, and generating the oscillation signals in response to the pulse signals, and if the bank-active signals are not received, oscillating the oscillation signals according to the level detection signal.