Dual panel-type organic electroluminescent device and method for fabricating the same

Abstract

A method of fabricating a dual panel-type active matrix organic electroluminescent device includes patterning a first metal layer to form a gate electrode, a gate line, a power line, a gate pad, and a power pad on a first substrate, forming a first insulating layer on the first substrate to cover the gate electrode, the gate pad, and the power pad, forming a semiconductor layer on the first insulating layer over the gate electrode, the semiconductor layer including an active layer of undoped amorphous silicon and an ohmic contact layer of doped amorphous silicon, forming source and drain electrodes, a data line, a first link electrode, and a data pad, wherein the source and drain electrodes are disposed on the ohmic contact layer, wherein the data line, the data pad, and the first link electrode are disposed on the first insulating layer, and wherein the first link electrode crosses the gate line, forming a channel within the active layer by etching a portion of the ohmic contact exposed between the source and drain electrodes to form a thin film transistor including the gate electrode, the semiconductor layer, the source electrode, and the drain electrode, forming a second insulating layer on the first insulating layer to cover the thin film transistor, the data line, and the data pad, forming a source contact hole, a drain contact hole, a data pad contact hole, a gate pad contact hole, and a power pad contact hole, wherein the source, drain and data pad contact holes penetrate the second insulating layer, and wherein the gate pad and power pad contact holes penetrate the first and second insulating layers, forming a connecting pattern on the pixel region on the second insulating layer using an insulating material, wherein the connecting pattern has a pillar shape and a height greater than a corresponding height of the thin film transistor, forming a connecting electrode, a power electrode, second link electrodes, a data pad terminal, a gate pad terminal, and a power pad terminal using a third metal layer.

1. A method of fabricating a dual panel-type active matrix organic electroluminescent device, comprising:
 patterning a first metal layer to form a gate electrode, a gate line, a power line, a gate pad, and a power pad on a first substrate; 
 forming a first insulating layer on the first substrate to cover the gate electrode, the gate pad, and the power pad; 
 forming a semiconductor layer on the first insulating layer over the gate electrode, the semiconductor layer including an active layer of undoped amorphous silicon and an ohmic contact layer of doped amorphous silicon; 
 forming source and drain electrodes, a data line, a first link electrode, and a data pad, wherein the source and drain electrodes are disposed on the ohmic contact layer, wherein the data line, the data pad, and the first link electrode are disposed on the first insulating layer, and wherein the first link electrode crosses the gate line; 
 forming a channel within the active layer by etching a portion of the ohmic contact exposed between the source and drain electrodes to form a thin film transistor including the gate electrode, the semiconductor layer, the source electrode, and the drain electrode; 
 forming a second insulating layer on the first insulating layer to cover the thin film transistor, the data line, and the data pad; 
 forming a source contact hole, a drain contact hole, a data pad contact hole, a gate pad contact hole, and a power pad contact hole, wherein the source, drain and data pad contact holes penetrate the second insulating layer, and wherein the gate pad and power pad contact holes penetrate the first and second insulating layers; 
 forming a connecting pattern on the pixel region on the second insulating layer using an insulating material, wherein the connecting pattern has a pillar shape and a height greater than a corresponding height of the thin film transistor; and 
 forming a connecting electrode, a power electrode, second link electrodes, a data pad terminal, a gate pad terminal, and a power pad terminal using a third metal layer. 
 
     
     
       2. The method according to  claim 1 , wherein the connecting electrode covers the connecting pattern and contacts the drain electrode via the drain contact hole. 
     
     
       3. The method according to  claim 1 , wherein the power electrode contacts the source electrode via the source contact hole and interconnects the thin film transistor to the power line. 
     
     
       4. The method according to  claim 1 , wherein the second link electrodes are disposed near the gate line and interconnect the power lines with the first link electrode along a first direction of the data line. 
     
     
       5. The method according to  claim 1 , wherein the data pad terminal, the gate pad terminal, and the power pad terminal are disposed to contact the data pad, the gate pad, and the power pad, respectively, via the data pad contact hole, via the gate pad contact hole, and via the power pad contact hole. 
     
     
       6. The method according to  claim 1 , wherein forming the gate and power line includes use of a first mask, wherein forming the semiconductor layer includes use of a second mask, wherein forming the source and drain electrodes includes use of a third mask, wherein forming the source and drain contact holes includes use of a fourth mask, wherein forming the connecting pattern includes use of a fifth mask, and wherein forming the connecting electrode includes use of a sixth mask. 
     
     
       7. The method according to  claim 1 , wherein the step of forming the source and drain electrodes includes forming a capacitor electrode over the power line and wherein the capacitor electrode constitutes a storage capacitor with the power line and the first and second insulating layers. 
     
     
       8. The method according to  claim 1 , further comprising an organic electroluminescent diode on a second substrate facing the first substrate, wherein the connecting electrode electrically interconnects the thin film transistor to the organic electroluminescent diode. 
     
     
       9. The method according to  claim 1 , wherein the gate line is disposed along a first direction, and the data and power lines are disposed a second direction and are spaced apart from each other to define the pixel region. 
     
     
       10. The method according to  claim 1 , wherein the insulating material for the connecting pattern includes organic insulating material. 
     
     
       11. A method of fabricating a dual panel-type active matrix organic electroluminescent device, comprising:
 patterning a first metal layer to form a gate electrode, a gate line, a power line, a gate pad, and a power pad on a first substrate; 
 forming a first insulating layer, a undoped amorphous silicon layer, a doped amorphous silicon layer, and a second metal layer sequentially on the first substrate to cover the gate electrode, the gate pad, and the power pad; 
 forming a photosensitive photoresist on the second metal layer; 
 disposing a first mask having a half-transmitting portion over the photosensitive photoresist; 
 patterning the undoped amorphous silicon layer, the doped amorphous silicon layer, and the second metal layer simultaneously using a diffraction exposure method using the first mask to form an active layer, an ohmic contact layer, a source electrode, a drain electrode, a data line, a first link electrode, and a data pad; 
 forming a channel in the active layer by etching a portion of the ohmic contact layer exposed between the source and drain electrodes to form a thin film transistor comprising the gate electrode, the active layer, the ohmic contact layer, the source electrode, and the drain electrode; 
 forming a second insulating layer on the first insulating layer to cover the thin film transistor, the data line, and the data pad; 
 forming a source contact hole, a drain contact hole, a data pad contact hole, a gate pad contact hole, and a power pad contact hole, wherein the source, drain, and data pad contact holes penetrate the second insulating layer, and wherein the gate pad and power pad contact holes penetrate the first and second insulating layers; 
 forming a connecting pattern on the pixel region on the second insulating layer using an insulating material, wherein the connecting pattern has a pillar shape and a height higher than a corresponding height of the thin film transistor; and 
 forming a connecting electrode, a power electrode, second link electrodes, a data pad terminal, a gate pad terminal, and a power pad terminal using a third metal layer. 
 
     
     
       12. The method according to  claim 11 , wherein the connecting electrode covers the connecting pattern and contacts the drain electrode via the drain contact hole. 
     
     
       13. The method according to  claim 11 , wherein the power electrode contacts the source electrode via the source contact hole and interconnects the thin film transistor to the power line. 
     
     
       14. The method according to  claim 11 , wherein the second link electrodes are disposed near the gate line and interconnect the power lines with the first link electrode. 
     
     
       15. The method according to  claim 11 , wherein the data pad terminal, the gate pad terminal, and the power pad terminal are disposed to contact the data pad, the gate pad, and the power pad, respectively, via the data pad contact hole, via the gate pad contact hole, and via the power pad contact hole. 
     
     
       16. The method according to  claim 11 , wherein forming the gate and power line includes use of a first mask, wherein patterning the undoped and doped amorphous silicon layer and the second metal layer includes use of a second mask, wherein forming the source and drain contact holes includes use of a third mask, wherein forming the connecting pattern includes use of a fourth mask, and wherein forming the connecting electrode includes use a fifth mask. 
     
     
       17. The method according to  claim 11 , wherein the step of patterning the undoped and doped amorphous silicon layers and the second metal layer includes forming a capacitor electrode over the power line. 
     
     
       18. The method according to  claim 17 , wherein the capacitor electrode constitutes a storage capacitor with the power line and the first and second insulating layers. 
     
     
       19. The method according to  claim 17 , wherein patterning the undoped and doped amorphous silicon layers and the second metal layer forms a plurality of semiconductor patterns beneath the data line, the first link electrode, and the data pad. 
     
     
       20. The method according to  claim 11 , further comprising an organic electroluminescent diode on a second substrate facing the first substrate, wherein the connecting electrode electrically interconnects the thin film transistor to the organic electroluminescent diode. 
     
     
       21. The method according to  claim 11 , wherein the gate line is disposed along a first direction, and the data and power lines are disposed along a second direction and are spaced apart from each other to define the pixel region. 
     
     
       22. The method according to  claim 11 , wherein the insulating material for the connecting pattern includes organic insulating material. 
     
     
       23. The method according to  claim 11 , wherein the photosensitive photoresist pattern is a positive type photoresist material. 
     
     
       24. The method according to  claim 11 , wherein the source and drain electrodes are disposed on the ohmic contact layer, and wherein the first link electrode crosses the gate line.