Systems and methods for simultaneously testing semiconductor memory devices

Abstract

A method for testing a memory cell array of a semiconductor memory device in a parallel bit test mode includes selecting first data from one of a plurality of memory regions in the memory array for output from the memory device via an input/output pad, and then selecting second data from another of the plurality of memory regions for output via the input/output pad. The first and second data can be selected from memory regions sharing a row select or a column select control line. Alternatively, one of the first and second data can be selected from memory regions sharing a row select control line, and the other can be selected from memory regions sharing a column select control line. Therefore, a parallel bit test can be performed using fewer input/output pads, and a larger number of semiconductor memory devices can simultaneously be tested. Related circuits are also discussed.

1. A method for testing a semiconductor memory device including nm memory cell regions for respectively outputting x-bit data when n word lines and m column selecting signal lines are selected, and each half of the nm memory cell regions is a first memory cell array and a second memory cell array, the method comprising:
 extending y-bit data received through y data I/O pads to (nm×x)-bit data to write the x-bit data to each of the nm memory cell regions in a test data write step; and 
 comparing the x-bit data output from each of the nm memory cell regions to generate nm-bit comparison result data, and sequentially outputting y-bit comparison result data selected by selecting, by y bits generated from the first memory cell array or from the second memory cell array, the nm-bit comparison result data in response to a control signal to the y data I/O pads, respectively, in a test data read step, 
 wherein n is an integer equal or greater than 2, wherein m is an integer equal or greater than 4, wherein x and y are integers greater than 1, wherein nm comprises n multiplied by m, and wherein y is less than nm. 
 
   
   
     2. The method of  claim 1 , wherein in the test data write step, when the x-bit data is written to the respective nm memory cell regions, the x-bit data written to the respective nm memory cell regions are same-bit data. 
   
   
     3. The method of  claim 1 , wherein the test data read step comprises:
 respectively comparing the x-bit data output from each of the nm memory cell regions to generate the nm-bit comparison result data in a comparing step; and 
 outputting the y-bit comparison result data selected by selecting, by y bits, the nm comparison result data in response to the control signal to the y data I/O pads in a selecting step. 
 
   
   
     4. A method for testing a semiconductor memory device including nm memory cell regions for respectively outputting x-bit data when n word lines and m column selecting signal lines are selected, the method comprising:
 extending y-bit data received through y data I/O pads to (nm×x)-bit data to write the x-bit data to each of the nm memory cell regions in a test data write step; and 
 comparing the x-bit data output from each of the nm memory cell regions to generate nm-bit comparison result data, grouping and outputting the nm-bit comparison result data into y groups by bit data generated with respect to corresponding n word lines or with respect to corresponding m column selecting signal lines in response to a control signal, and outputting y-bit comparison result data generated by respectively comparing the y grouped bit data through the y data I/O pads in a test data read step, 
 wherein n is an integer equal or greater than 2, wherein m is an integer equal or greater than 4, wherein x and y are integers greater than 1, wherein nm comprises n multiplied by m, and wherein y is less than nm. 
 
   
   
     5. The method of  claim 4 , wherein in the test data write step, when x-bit data are written to the respective nm memory cell regions, the x-bit data written to the nm memory cell regions are same-bit data. 
   
   
     6. The method of  claim 5 , wherein the test data read step comprises:
 respectively comparing the x-bit data output from each of the nm memory cell regions in a first comparing step; 
 grouping and outputting the nm-bit comparison result data into y groups by bit data generated with respect to corresponding n word lines or with respect to corresponding m column selecting signal lines in response to a control signal; and 
 outputting the y-bit comparison result data generated by respectively comparing the y grouped bit data through the y data I/O pads. 
 
   
   
     7. The method of  claim 6 , wherein y is set to at least n when n is greater than m and is set to at least m when m is greater than n. 
   
   
     8. A semiconductor memory device, comprising:
 nm memory cell regions configured to respectively output x-bit data when n word lines and m column selecting signal lines are selected, and each half of the nm memory cell regions is a first memory cell array and a second memory cell array; 
 a test data write circuit configured to extend y-bit data received through y data I/O pads to (nm×x)-bit data to write the x-bit data to each of the mu memory cell regions; and 
 a test data read circuit configured to compare the x-bit data output from each of the nm memory cell region to generate nm-bit comparison result data, and sequentially output y-bit comparison result data selected by selecting, by y bits generated from the first memory cell array or from the second memory cell array, the nm-bit comparison result data in response to a control signal to the y data I/O pads, respectively, 
 wherein n is an integer equal or greater than 2, wherein m is an integer equal or greater than 4, wherein x and y are integers greater than 1, wherein nm comprises n multiplied by m, and wherein y is less than nm. 
 
   
   
     9. The device of  claim 8 , wherein in the test data write circuit, when x-bit data is written to the respective nm memory cell regions, the x-bit data written to the respective nm memory cell regions are same-bit data. 
   
   
     10. The device of  claim 8 , wherein the test data read circuit includes:
 a comparator configured to respectively compare the x-bit data output from each of the nm memory cell regions to generate the nm-bit comparison result data; and 
 a selecting circuit configured to output the y-bit comparison result data selected by selecting, by y bits generated from the first memory cell array or from the second memory cell array, the nm comparison result data in response to the control signal to the y data I/O pads. 
 
   
   
     11. A semiconductor memory device, comprising:
 nm memory cell regions configured to respectively output x-bit data when n word lines and m column selecting signal lines are selected; 
 a test data write circuit configured to extend y-bit data received through y data I/O pads to (nm×x)-bit data to write the x-bit data to each of the nm memory cell regions; and 
 a test data read circuit configured to compare the x-bit data output from each of the nm memory cell regions to generate nm-bit comparison result data, group and output the nm-bit comparison result data into y groups by bit data generated with respect to corresponding n word lines or with respect to corresponding m column selecting signal lines in response to a control signal, and output y-bit comparison result data generated by respectively comparing the y grouped bit data through the y data I/O pads, 
 wherein n is an integer equal or greater than 2, wherein m is an integer equal or greater than 4, wherein x and y are integers greater than 1, wherein nm, comprises n multiplied by m, and wherein y is less than nm. 
 
   
   
     12. The device of  claim 11 , wherein the test data read circuit includes:
 a first comparator configured to respectively compare the x-bit data output from each of the nm memory cell regions; 
 a selecting circuit configured to group and output the nm-bit comparison result data into y groups by bit data generated with respect to corresponding n word lines or with respect to corresponding m column selecting signal lines in response to the control signal; and 
 a second comparator configured to output the y-bit comparison result data generated by respectively comparing the y grouped bit data through the y data I/O pads. 
 
   
   
     13. The device of  claim 12 , wherein y is set to at least n when n is greater than m and is set to at least in when m is greater than n.