Direct digital synthesizer with variable reference for improved spurious performance

Abstract

Improvement of quantization errors that arise in a delay line with finite resolution. A direct digital synthesizer (DDS), which contains a numerically controlled oscillator (NCO) and a digital-to-phase converter (DPC), is placed in the feedback loop of a phase locked loop (PLL). The DDS is used as a fractional divider of the voltage controlled oscillator (VCO) frequency, such that the reference frequency of the DDS is made variable. Alignment of the edges provided by the DDS delay line may then be adjusted. Mismatch errors in the DDS delay line are reduced by utilizing independently tunable delay elements.

1. A structure for reducing mismatch error in a delay line, comprising:
 a delay line with a plurality of tap outputs; 
 a plurality of independently programmable delay elements each placed at a respective one of the plurality of tap outputs; and 
 wherein the independently programmable delay elements are operable to be independently adjusted to compensate for mismatch error at their respective tap output of the plurality of tap outputs. 
 
     
     
       2. The structure of  claim 1 , wherein the delay line performs an inversion function. 
     
     
       3. The structure of  claim 2 , wherein the plurality of independently programmable delay elements perform the inversion function of the delay line. 
     
     
       4. The structure of  claim 3 , further comprising two or more of the independently programmable delay elements to yield a non-inverting function of the structure. 
     
     
       5. The structure of  claim 1 , wherein the plurality of independently programmable delay elements are coupled in a differential configuration within a cross-coupled delay line structure. 
     
     
       6. The structure of  claim 1 , wherein the independently programmable delay elements are weighted in accordance with desired programmable steps.