Pipeline A/D converter converting analog signal to digital signal

Abstract

A first stage of a pipeline A/D converter is configured to output a sub analog signal at a level within a predetermined output voltage range even if a level of an input analog signal exceeds a predetermined input voltage range. Therefore, as compared with an example where a limiter circuit is provided on an input side of each stage, a pipeline A/D converter occupying a small area, consuming low power, and having small errors can be provided.

1. A pipeline A/D converter converting an analog signal to a digital signal, comprising:
 first to Nth stages that are cascaded, where N is an integer not smaller than 2; and 
 an error correction circuit generating said digital signal based on sub digital signals output from the first to Nth stages; 
 said first stage including a first sub ADC converting said analog signal to the sub digital signal and providing the sub digital signal to said error correction circuit and a first sub DAC outputting to said second stage, a sub analog signal at a level in accordance with said analog signal and the sub digital signal generated in said first sub ADC, 
 each of said second to said N−1th stages including a second sub ADC converting the sub analog signal provided from a preceding stage to the sub digital signal and providing the sub digital signal to said error correction circuit and a second sub DAC outputting to a subsequent stage, a sub analog signal at a level in accordance with the sub analog signal provided from the preceding stage and the sub digital signal generated in said second sub ADC, 
 said Nth stage including a third sub ADC converting the sub analog signal provided from the preceding stage to the sub digital signal and providing the sub digital signal to said error correction circuit, 
 said first sub DAC being configured to output the sub analog signal at a level within a predetermined output voltage range even if the level of said analog signal exceeds a predetermined input voltage range, 
 said first stage further including an overflow detection circuit outputting an overflow detection signal in response to the level of said analog signal exceeding said predetermined input voltage range, said overflow detection circuit including 
 a voltage-division circuit dividing a first voltage to generate a plurality of second voltages, and 
 a comparator comparing a first level corresponding to said analog signal with a second level corresponding to a sum of said first voltage and said second voltage and outputting said overflow detection signal in response to said first level exceeding said second level, and 
 said first sub DAC outputs the sub analog signal at a prescribed level within said predetermined output voltage range, in response to said overflow detection signal. 
 
     
     
       2. The pipeline A/D converter according to  claim 1  wherein
 each of said analog signal and said sub analog signal is a differential signal. 
 
     
     
       3. A pipeline A/D converter converting an analog signal to a digital signal, comprising:
 first to Nth stages that are cascaded, where N is an integer not smaller than 2; and 
 an error correction circuit generating said digital signal based on sub digital signals output from the first to Nth stages; 
 said first stage including a first sub ADC converting said analog signal to the sub digital signal and providing the sub digital signal to said error correction circuit and a first sub DAC outputting to said second stage, a sub analog signal at a level in accordance with said analog signal and the sub digital signal generated in said first sub ADC, 
 each of said second to said N−1th stages including a second sub ADC converting the sub analog signal provided from a preceding stage to the sub digital signal and providing the sub digital signal to said error correction circuit and a second sub DAC outputting to a subsequent stage, a sub analog signal at a level in accordance with the sub analog signal provided from the preceding stage and the sub digital signal generated in said second sub ADC, 
 said Nth stage including a third sub ADC converting the sub analog signal provided from the preceding stage to the sub digital signal and providing the sub digital signal to said error correction circuit, 
 said first sub DAC is configured to output the sub analog signal at a level within a predetermined output voltage range even if the level of said analog signal exceeds a predetermined input voltage range, 
 said first sub ADC includes 
 a reference voltage generation circuit dividing a differential voltage between first and second voltages to generate first to nth reference voltages, where n is an integer not smaller than 2, 
 first to nth comparators comparing the level of said analog signal with said first to nth reference voltages respectively, and 
 an encoder outputting the sub digital signal based on a result of comparison by said first to nth comparators, 
 said nth reference voltage represents an upper limit of said predetermined input voltage range, 
 said first sub DAC outputs the sub analog signal based on the level of said analog signal and the result of comparison by said first to nth comparators, and 
 a transfer function of said first stage has n turning points. 
 
     
     
       4. The pipeline A/D converter according to  claim 3 , wherein
 said first sub DAC includes 
 first to nth capacitors provided in correspondence with said first to nth comparators respectively, 
 a first switch provided in correspondence with each capacitor and providing said analog signal to one terminal of a corresponding capacitor during a first period, 
 a second switch provided in correspondence with each capacitor and selectively providing any one voltage out of said first and second voltages to one terminal of the corresponding capacitor during a second period, based on a result of comparison by the corresponding comparator, and 
 an amplifier having an input terminal connected to other terminals of said first to nth capacitors and outputting said sub analog signal. 
 
     
     
       5. The pipeline A/D converter according to  claim 3 , wherein
 said first stage further includes an overflow detection circuit outputting an overflow detection signal in response to the level of said analog signal exceeding the n+1th reference voltage higher than said first to nth reference voltages, and 
 said first sub DAC outputs the sub analog signal at a prescribed level within said predetermined output voltage range, in response to said overflow detection signal. 
 
     
     
       6. The pipeline A/D converter according to  claim 5 , wherein
 said overflow detection circuit includes a comparator comparing a first level corresponding to said analog signal with a second level based on said first and second voltages and an output voltage of said reference voltage generation circuit and outputting said overflow detection signal in response to said first level exceeding said second level. 
 
     
     
       7. The pipeline A/D converter according to  claim 3 , wherein said n is 8. 
     
     
       8. The pipeline A/D converter according to  claim 3 , wherein said n is 4. 
     
     
       9. A pipeline A/D converter converting an analog signal to a digital signal, comprising:
 first to Nth stages that are cascaded, where N is an integer not smaller than 2; and 
 an error correction circuit generating said digital signal based on sub digital signals output from the first to Nth stages; 
 said first stage including a first sub ADC converting said analog signal to the sub digital signal and providing the sub digital signal to said error correction circuit and a first sub DAC outputting to said second stage, a sub analog signal at a level in accordance with said analog signal and the sub digital signal generated in said first sub ADC, 
 each of said second to said N−1th stages including a second sub ADC converting the sub analog signal provided from a preceding stage to the sub digital signal and providing the sub digital signal to said error correction circuit and a second sub DAC outputting to a subsequent stage, a sub analog signal at a level in accordance with the sub analog signal provided from the preceding stage and the sub digital signal generated in said second sub ADC, 
 said Nth stage including a third sub ADC converting the sub analog signal provided from the preceding stage to the sub digital signal and providing the sub digital signal to said error correction circuit, 
 said first sub DAC is configured to output the sub analog signal at a level within a predetermined output voltage range even if the level of said analog signal exceeds a predetermined input voltage range, 
 a transfer function of said first stage includes 
 six first turning points corresponding to first to sixth reference voltages for generating a signal of 2.75 bits among the sub digital signals output from said first sub ADC, respectively, and 
 a second turning point corresponding to a seventh reference voltage higher than said first to sixth reference voltages for generating a signal of 0.25 bit among the sub digital signals output from said first sub ADC. 
 
     
     
       10. The pipeline A/D converter according to  claim 9 , wherein
 the transfer function of said first stage further includes a third turning point corresponding to an eighth reference voltage higher than said seventh reference voltage, and 
 if the level of said analog signal is higher than said eighth reference voltage, the sub analog signal output from said first sub DAC is set to 0 level. 
 
     
     
       11. A pipeline A/D converter converting an analog signal to a digital signal, comprising:
 first to Nth stages that are cascaded, where N is an integer not smaller than 2; and 
 an error correction circuit generating said digital signal based on sub digital signals output from the first to Nth stages; 
 said first stage including a first sub ADC converting said analog signal to the sub digital signal and providing the sub digital signal to said error correction circuit and a first sub DAC outputting to said second stage, a sub analog signal at a level in accordance with said analog signal and the sub digital signal generated in said first sub ADC, 
 each of said second to said N−1th stages including a second sub ADC converting the sub analog signal provided from a preceding stage to the sub digital signal and providing the sub digital signal to said error correction circuit and a second sub DAC outputting to a subsequent stage, a sub analog signal at a level in accordance with the sub analog signal provided from the preceding stage and the sub digital signal generated in said second sub ADC, 
 said Nth stage including a third sub ADC converting the sub analog signal provided from the preceding stage to the sub digital signal and providing the sub digital signal to said error correction circuit, 
 said first sub DAC is configured to output the sub analog signal at a level within a predetermined output voltage range even if the level of said analog signal exceeds a predetermined input voltage range, 
 a transfer function of said first stage includes 
 two first turning points corresponding to first and second reference voltages for generating a signal of 1.5 bit among the sub digital signals output from said first sub ADC, respectively, and 
 a second turning point corresponding to a third reference voltage higher than said first and second reference voltages for generating a signal of 0.5 bit among the sub digital signals output from said first sub ADC. 
 
     
     
       12. The pipeline A/D converter according to  claim 11 , wherein
 the transfer function of said first stage further includes a third turning point corresponding to a fourth reference voltage higher than said third reference voltage, and 
 if the level of said analog signal is higher than said fourth reference voltage, the sub analog signal output from said first sub DAC is set to 0 level. 
 
     
     
       13. A pipeline A/D converter converting an analog signal to a digital signal, comprising:
 first to Nth stages that are cascaded, where N is an integer not smaller than 2; and 
 an error correction circuit generating said digital signal based on sub digital signals output from the first to Nth stages; 
 said first stage including a first sub ADC converting said analog signal to the sub digital signal and providing the sub digital signal to said error correction circuit and a first sub DAC outputting to said second stage, a sub analog signal at a level in accordance with said analog signal and the sub digital signal generated in said first sub ADC, 
 each of said second to said N−1th stages including a second sub ADC converting the sub analog signal provided from a preceding stage to the sub digital signal and providing the sub digital signal to said error correction circuit and a second sub DAC outputting to a subsequent stage, a sub analog signal at a level in accordance with the sub analog signal provided from the preceding stage and the sub digital signal generated in said second sub ADC, 
 said Nth stage including a third sub ADC converting the sub analog signal provided from the preceding stage to the sub digital signal and providing the sub digital signal to said error correction circuit, 
 said first sub DAC is configured to output the sub analog signal at a level within a predetermined output voltage range even if the level of said analog signal exceeds a predetermined input voltage range, 
 each of said second to N−1th stages has a lateral shared amplifier configuration and includes a fourth sub ADC converting the sub analog signal provided from the preceding stage to the sub digital signal and providing the sub digital signal to said error correction circuit, and 
 said second sub DAC outputs to the subsequent stage, the sub analog signal at a level in accordance with the sub analog signal provided from the preceding stage and the sub digital signal generated in said second sub ADC during a certain period, and outputs to the subsequent stage, the sub analog signal at a level in accordance with the sub analog signal provided from the preceding stage and the sub digital signal generated in said fourth sub ADC during a next period. 
 
     
     
       14. A pipeline A/D converter converting an analog signal to a digital signal, comprising:
 first to Nth stages that are cascaded, where N is an integer not smaller than 2; and 
 an error correction circuit generating said digital signal based on sub digital signals output from the first to Nth stages; 
 said first stage including a first sub ADC converting said analog signal to the sub digital signal and providing the sub digital signal to said error correction circuit and a first sub DAC outputting to said second stage, a sub analog signal at a level in accordance with said analog signal and the sub digital signal generated in said first sub ADC, 
 each of said second to said N−1th stages including a second sub ADC converting the sub analog signal provided from a preceding stage to the sub digital signal and providing the sub digital signal to said error correction circuit and a second sub DAC outputting to a subsequent stage, a sub analog signal at a level in accordance with the sub analog signal provided from the preceding stage and the sub digital signal generated in said second sub ADC, 
 said Nth stage including a third sub ADC converting the sub analog signal provided from the preceding stage to the sub digital signal and providing the sub digital signal to said error correction circuit, 
 said first sub DAC is configured to output the sub analog signal at a level within a predetermined output voltage range even if the level of said analog signal exceeds a predetermined input voltage range, 
 each of said second to N−1th stages has a vertical shared amplifier configuration and includes a fourth sub ADC converting the sub analog signal provided from said second sub DAC to the sub digital signal and providing the sub digital signal to said error correction circuit, and 
 said second sub DAC outputs to said fourth sub ADC, the sub analog signal at a level in accordance with the sub analog signal provided from the preceding stage and the sub digital signal generated in said second sub ADC during a certain period, and outputs to the subsequent stage, the sub analog signal at a level in accordance with the generated sub analog signal and the sub digital signal generated in said fourth sub ADC during a next period.