Method and apparatus for extending decoding time in an iterative decoder using input codeword pipelining

Abstract

A decoder architecture and method for implementing a decoder are provided. In one implementation, the decoder architecture includes an input buffer configured to receive a plurality of codewords to be processed, and includes an iterative decoder configured to receive a first codeword from the input buffer and process the first codeword. The iterative decoder processes the first codeword only for an amount of time required for the first codeword to become substantially error free. The decoder architecture further includes logic coupled to each of the iterative decoder and the input buffer. The logic is configured to determine when the first codeword processed by the decoder becomes substantially error free. The logic further generates a signal for loading a second codeword from the input buffer into the iterative decoder responsive to the logic determining when the first codeword becomes substantially error free.

1. A decoder architecture comprising:
 an input buffer configured to receive a plurality of codewords to be processed, wherein the input buffer is configured to receive each of the plurality of codewords at a pre-determined fixed rate; 
 a decoder configured to receive a first codeword from the input buffer and process the first codeword, the decoder processing the first codeword only for an amount of time required for the first codeword to become substantially error free, wherein an average decoding speed of the decoder is set such that an average read speed of the decoder from the input buffer is faster than the pre-determined fixed rate of receiving the plurality of codewords in the input buffer; and 
 logic in communication with each of the decoder and the input buffer, the logic configured to determine when the first codeword processed by the decoder becomes substantially error free, wherein the logic generates a signal for loading a second codeword from the input buffer into the decoder responsive to the logic determining that the first codeword has become substantially error free. 
 
   
   
     2. The decoder architecture of  claim 1 , wherein a time difference between the pre-determined fixed rate at which the input buffer receives each of the plurality of codewords and the average read speed of the decoder is accumulated over multiple codewords, the accumulated time difference providing additional time for the decoder to decode a codeword requiring longer than the average decoding speed to become substantially error free. 
   
   
     3. The decoder architecture of  claim 1 , wherein the pre-determined fixed rate corresponds to a value between a maximum time required for the decoder to process a worst case codeword and a minimum time required to decode each of a majority of the plurality of codewords. 
   
   
     4. The decoder architecture of  claim 1 , further comprising a counter to limit a maximum amount of time for a given codeword to be processed by the decoder. 
   
   
     5. The decoder architecture of  claim 4 , further comprising an output buffer configured to receive codewords from the decoder and output each codeword at a rate synchronized to the pre-determined fixed rate. 
   
   
     6. The decoder architecture of  claim 1 , wherein the decoder is an iterative decoder. 
   
   
     7. The decoder architecture of  claim 6 , wherein the iterative decoder comprises one of a low density parity check (LDPC) decoder, a Hamming decoder, or a Turbo decoder. 
   
   
     8. The decoder architecture of  claim 6 , wherein the logic determines that the first codeword processed by the decoder has become substantially error free upon the first codeword passing all parity checks of an H matrix associated with the iterative decoder. 
   
   
     9. The decoder architecture of  claim 1  wherein the decoder receives the plurality of codewords at a variable rate from the input buffer. 
   
   
     10. A method for decoding a plurality of codewords, the method comprising:
 loading a plurality of codewords to be processed into an input buffer, wherein the loading the plurality of codewords into the input buffer is at a pre-determined fixed rate; 
 transferring a first codeword from the input buffer to a decoder; 
 processing the first codeword in the decoder, wherein an average decoding speed of the decoder is set such that an average read speed of the decoder from the input buffer is faster than the pre-determined fixed rate of loading the plurality of codewords into the input buffer; 
 determining when the first codeword processed by the decoder becomes substantially error free; and 
 generating a signal for loading a second codeword from the input buffer into the decoder responsive to a determination that the first codeword has become substantially error free. 
 
   
   
     11. The method of  claim 10 , wherein a time difference between the pre-determined fixed rate at which the input buffer receives each of the plurality of codewords and the average read speed of the decoder is accumulated over multiple codewords, the accumulated time difference providing additional time for the decoder to decode a codeword that requires longer than the average decoding speed to become substantially error free. 
   
   
     12. The method of  claim 10 , wherein the pre-determined fixed rate corresponds to a value between a maximum time required for the decoder to process a worst case codeword and a minimum time required to decode each of a majority of the plurality of codewords. 
   
   
     13. The method of  claim 12 , wherein the maximum time required for the decoder to process a worst case codeword and the minimum time required to decode each of a majority of the plurality of codewords are determined empirically based on application requirements. 
   
   
     14. The method of  claim 10 , further comprising limiting a maximum amount of time for a given codeword to be processed by the decoder. 
   
   
     15. The method of  claim 14 , further comprising providing an output buffer in communication with the decoder, the output buffer receiving codewords from the decoder and outputting each codeword at a rate synchronized to the pre-determined fixed rate. 
   
   
     16. The method of  claim 10 , wherein the decoder is an iterative decoder. 
   
   
     17. The method of  claim 16 , wherein the iterative decoder comprises one of a low density parity check (LDPC) decoder, a Hamming decoder, or a Turbo decoder. 
   
   
     18. The method of  claim 16 , wherein determining when the first codeword processed by the decoder becomes substantially error free comprises determining that the first codeword processed by the decoder has become substantially error free upon the first codeword passing all parity checks of an H matrix associated with the iterative decoder. 
   
   
     19. The method of  claim 10  wherein the plurality of codewords are transferred from the input buffer to the decoder at a variable rate.