Fractional-N phase locked loop

Abstract

An apparatus and method is disclosed to substantially reduce phase noise introduced in fractional-N phase-locked loop (PLL) through feedback modulation. A fractional frequency divider is introduced in the feedback path of the PLL to generate a true fractional division factor with finite fractional steps to increase the resolution of the PLL by a factor equal to the inverse of the finite step size in the fractional frequency divider. Increasing the resolution of the PLL reduces phase noise. The fractional frequency divider uses the true fractional division factor to divide the frequency of a single output of a multi-phased voltage controlled oscillator (VCO) by the fractional division factor to match the frequency of the divided feedback signal to frequency a reference signal. The fractional frequency divider incrementally selects among all the outputs of the multi-phased VCO according to either a forward phase shifting operation or a backward phase shifting operation to generate a true fractional division factor.

1. A phase-locked loop (PLL), configured to receive a reference signal, comprising:
 a phase detector configured to output an error signal based on a difference between a divided feedback signal and the reference signal; 
 a voltage controlled oscillator configured to output a plurality of voltage controlled oscillator outputs based on the error signal; and 
 a fractional frequency divider configured to arrange the plurality of voltage controlled oscillator outputs in one or more pairs of voltage controlled oscillator outputs, each voltage controlled oscillator output from the one or more pairs being substantially offset in phase by π, wherein the fractional frequency divider is configured to generate the divided feedback signal by switching from a first voltage controlled oscillator output from the plurality of voltage controlled oscillator outputs to a second voltage controlled oscillator output from the plurality of voltage controlled oscillator outputs, and 
 wherein a phase offset of the first voltage controlled oscillator output is greater than a phase offset of the second voltage controlled oscillator output. 
 
     
     
       2. The PLL of  claim 1 , further comprising:
 a dithering modulator coupled to the fractional frequency divider, wherein the dithering modulator is configured to dither a divide value of the fractional frequency divider between a first fractional value and a second fractional value. 
 
     
     
       3. The PLL of  claim 2 , wherein the dithering modulator is a sigma-delta modulator. 
     
     
       4. The PLL of  claim 1 , wherein the fractional frequency divider is configured to incrementally switch from the first voltage controlled oscillator output to the second voltage controlled oscillator output. 
     
     
       5. The PLL of  claim 1 , wherein the fractional frequency divider is configured to switch among the plurality of voltage controlled oscillator outputs in a counter-clockwise manner. 
     
     
       6. The PLL of  claim 1 , wherein the fractional frequency divider is configured to switch from the first voltage controlled oscillator output to the second voltage controlled oscillator output based on a falling edge of the first voltage controlled oscillator output. 
     
     
       7. The PLL of  claim 1 , wherein the fractional frequency divider comprises:
 a phase rotator configured to generate a clock signal by switching from the first voltage controlled oscillator output to the second voltage controlled oscillator output; and 
 an integer divider configured to generate the divided feedback signal based upon the clock signal. 
 
     
     
       8. The PLL of  claim 7 , wherein the phase rotator comprises:
 a multiplexer control circuit configured to generate a control signal based upon a control word, wherein the control word is configured to determine a number of transitions required to generate the divided feedback signal; and 
 a multiplexer configured to generate the clock signal by switching from the first voltage controlled oscillator output to the second voltage controlled oscillator output based upon the control signal. 
 
     
     
       9. A phase-locked loop (PLL), configured to receive a reference signal, comprising:
 a phase detector configured to output an error signal based on a difference between a divided feedback signal and the reference signal; 
 a voltage controlled oscillator configured to output a plurality of voltage controlled oscillator outputs based on the error signal; and 
 a fractional frequency divider configured to arrange the plurality of voltage controlled oscillator outputs in one or more pairs of voltage controlled oscillator outputs, each voltage controlled oscillator output from the one or more pairs being substantially offset in phase by π, wherein the fractional frequency divider is configured to generate the divided feedback signal by switching from a first voltage controlled oscillator output from the plurality of voltage controlled oscillator outputs to a second voltage controlled oscillator output from the plurality of voltage controlled oscillator outputs, and 
 wherein a phase offset of the first voltage controlled oscillator output is lesser than a phase offset of the second voltage controlled oscillator output. 
 
     
     
       10. The PLL of  claim 9 , further comprising:
 a dithering modulator coupled to the fractional frequency divider, wherein the dithering modulator is configured to dither a divide value of the fractional frequency divider between a first fractional value and a second fractional value. 
 
     
     
       11. The PLL of  claim 10 , wherein the dithering modulator is a sigma-delta modulator. 
     
     
       12. The PLL of  claim 9 , wherein the fractional frequency divider is configured to incrementally switch from the first voltage controlled oscillator output to the second voltage controlled oscillator output. 
     
     
       13. The PLL of  claim 9 , wherein the fractional frequency divider is configured to switch among the plurality of voltage controlled oscillator outputs in a clockwise manner. 
     
     
       14. The PLL of  claim 9 , wherein the fractional frequency divider is configured to switch from the first voltage controlled oscillator output to the second voltage controlled oscillator output based on a rising edge of the first voltage controlled oscillator output. 
     
     
       15. The PLL of  claim 9 , wherein the fractional frequency divider comprises:
 a phase rotator configured to generate a clock signal by switching from the first voltage controlled oscillator output to the second voltage controlled oscillator output; and 
 an integer divider configured to generate the divided feedback signal based upon the clock signal. 
 
     
     
       16. The PLL of  claim 15 , wherein the phase rotator comprises:
 a multiplexer control circuit configured to generate a control signal based upon a control word, wherein the control word is configured to determine a number of transitions required to generate the divided feedback signal; and 
 a multiplexer configured to generate the clock signal by switching from the first voltage controlled oscillator output to the second voltage controlled oscillator output based upon the control signal. 
 
     
     
       17. A phase-locked loop (PLL), configured to receive a reference signal, comprising:
 a phase detector configured to output an error signal based on a difference between a divided feedback signal and the reference signal; 
 a voltage controlled oscillator configured to output a plurality of voltage controlled oscillator outputs based on the error signal; and 
 a fractional frequency divider configured to arrange the plurality of voltage controlled oscillator outputs in one or more pairs of voltage controlled oscillator outputs, each voltage controlled oscillator output from the one or more pairs being substantially offset in phase by π, wherein the fractional frequency divider is configured to generate at least one of a first fractional value and a second fractional value by switching among the plurality of voltage controlled oscillator outputs, and to dither a divide value of the fractional frequency divider between the first fractional value and the second fractional value to produce the divided feedback signal. 
 
     
     
       18. The PLL of  claim 17 , further comprising:
 a dithering modulator coupled to the fractional frequency divider, wherein the dithering modulator is configured to produce a divide control signal, wherein the fractional frequency divider is configured to dither the divide value based upon the divide control signal. 
 
     
     
       19. The PLL of  claim 18 , wherein the dithering modulator is configured to produce the divide control signal based upon a fractional control signal. 
     
     
       20. The PLL of  claim 17 , wherein at least one of the first fractional value and the second fractional value is generated by switching from a first voltage controlled oscillator output from the plurality of voltage controlled oscillator outputs to a second voltage controlled oscillator output from the plurality of voltage controlled oscillator outputs. 
     
     
       21. The PLL of  claim 20 , wherein a phase offset of the first voltage controlled oscillator output is greater than a phase offset of the second voltage controlled oscillator output. 
     
     
       22. The PLL of  claim 20 , wherein a phase offset of the first voltage controlled oscillator output is lesser than a phase offset of the second voltage controlled oscillator output. 
     
     
       23. The PLL of  claim 17 , wherein the plurality of voltage controlled oscillator outputs includes a plurality of phase offsets. 
     
     
       24. The PLL of  claim 23 , wherein each one of the voltage controlled oscillator outputs in the plurality of voltage controlled oscillator outputs has a corresponding phase offset in the plurality of phase offsets. 
     
     
       25. The PLL of  claim 24 , wherein a sum of all the corresponding phases of the voltage controlled oscillator outputs in the plurality of voltage controlled oscillator outputs substantially equals 2π. 
     
     
       26. The PLL of  claim 25 , wherein at least one of the first fractional value and the second fractional value is generated by switching from a first voltage controlled oscillator output from the plurality of voltage controlled oscillator outputs to a second voltage controlled oscillator output from the plurality of voltage controlled oscillator outputs. 
     
     
       27. The PLL of  claim 25 , wherein at least one of the first fractional value and the second fractional value is generated by switching from a first voltage controlled oscillator output from the plurality of voltage controlled oscillator outputs having a greatest phase offset to a second voltage controlled oscillator output from the plurality of voltage controlled oscillator outputs having a least phase offset. 
     
     
       28. The PLL of  claim 25 , wherein at least one of the first fractional value and the second fractional value is generated by switching from a first voltage controlled oscillator output from the plurality of voltage controlled oscillator outputs having a least phase offset to a second voltage controlled oscillator output from the plurality of voltage controlled oscillator outputs having a greatest phase offset. 
     
     
       29. The PLL of  claim 17 , wherein fractional frequency divider comprises:
 a phase rotator configured to generate a clock signal by switching from the first voltage controlled oscillator output to the second voltage controlled oscillator output; and 
 an integer divider configured to generate the divided feedback signal based upon the clock signal. 
 
     
     
       30. The PLL of  claim 29 , wherein the phase rotator comprises:
 a multiplexer control circuit configured to generate a control signal based upon a control word, wherein the control word is configured to determine a number of transitions required to generate the divided feedback signal; and 
 a multiplexer configured to generate the clock signal by switching from the first voltage controlled oscillator output to the second voltage controlled oscillator output based upon the control signal. 
 
     
     
       31. A phase-locked loop (PLL), configured to receive a reference signal, comprising:
 a phase detector configured to output an error signal based on a difference between a divided feedback signal and the reference signal; 
 a voltage controlled oscillator configured to output a plurality of voltage controlled oscillator outputs based on the error signal; 
 means for arranging the plurality of voltage controlled oscillator outputs in one or more pairs of voltage controlled oscillator outputs, each voltage controlled oscillator output from the one or more pairs being substantially offset in phase by π; and 
 means for generating the divided feedback signal by switching from a first voltage controlled oscillator output from the plurality of voltage controlled oscillator outputs to a second voltage controlled oscillator output from the plurality of voltage controlled oscillator outputs, 
 wherein a phase offset of the first voltage controlled oscillator output is greater than a phase offset of the second voltage controlled oscillator output. 
 
     
     
       32. The PLL of  claim 31 , wherein the for generating the divided feedback signal is configured to incrementally switch from the first voltage controlled oscillator output to the second voltage controlled oscillator output. 
     
     
       33. The PLL of  claim 31 , wherein the means for generating the divided feedback signal is configured to switch among the plurality of voltage controlled oscillator outputs in a counter-clockwise manner. 
     
     
       34. The PLL of  claim 31 , wherein means for generating the divided feedback signal is configured to switch from the first voltage controlled oscillator output to the second voltage controlled oscillator output based on a falling edge of the first voltage controlled oscillator output. 
     
     
       35. A phase-locked loop (PLL), configured to receive a reference signal, comprising:
 a phase detector configured to output an error signal based on a difference between a divided feedback signal and the reference signal; 
 a voltage controlled oscillator configured to output a plurality of voltage controlled oscillator outputs based on the error signal; 
 means for arranging the plurality of voltage controlled oscillator outputs in one or more pairs of voltage controlled oscillator outputs, each voltage controlled oscillator output from the one or more pairs being substantially offset in phase by π; and 
 means for generating the divided feedback signal by switching from a first voltage controlled oscillator output from the plurality of voltage controlled oscillator outputs to a second voltage controlled oscillator output from the plurality of voltage controlled oscillator outputs, 
 wherein a phase offset of the first voltage controlled oscillator output is lesser than a phase offset of the second voltage controlled oscillator output. 
 
     
     
       36. The PLL of  claim 35 , wherein the means for generating the divided feedback signal is configured to incrementally switch from the first voltage controlled oscillator output to the second voltage controlled oscillator output. 
     
     
       37. The PLL of  claim 35 , wherein the for generating the divided feedback signal is configured to switch among the plurality of voltage controlled oscillator outputs in a clockwise manner. 
     
     
       38. The PLL of  claim 35 , wherein the for generating the divided feedback signal is configured to switch from the first voltage controlled oscillator output to the second voltage controlled oscillator output based on a rising edge of the first voltage controlled oscillator output. 
     
     
       39. A method to phase lock a corresponding output of a voltage controlled oscillator having a plurality of voltage controlled oscillator outputs to a reference signal, the method comprises the steps of:
 comparing a divided feedback signal to the reference signal to produce an error signal; 
 adjusting a frequency of a voltage controlled oscillator based upon the error signal until the frequency of the voltage controlled oscillator is matched to the reference signal; 
 arranging the plurality of voltage controlled oscillator outputs in one or more pairs of voltage controlled oscillator outputs, each voltage controlled oscillator output from the one or more pairs being substantially offset in phase by π, and 
 generating the divided feedback signal by switching among the plurality of voltage controlled oscillator outputs. 
 
     
     
       40. The method of  claim 39 , wherein the step of comparing the divided feedback signal to the reference signal further comprises:
 comparing a phase of the divided feedback signal to a phase of the reference signal. 
 
     
     
       41. The method of  claim 39 , adjusting a frequency of a voltage controlled oscillator further comprises:
 adjusting the frequency of the voltage controlled oscillator until the frequency of the voltage controlled oscillator is matched to the reference signal in frequency and phase. 
 
     
     
       42. The method of  claim 39 , wherein the step of generating the divided feedback signal comprises:
 incrementally switching from a first voltage controlled oscillator output from the plurality of voltage controlled oscillator outputs to a second voltage controlled oscillator output from the plurality of voltage controlled oscillator outputs. 
 
     
     
       43. The method of  claim 39 , wherein the step of generating the divided feedback signal comprises:
 incrementally switching from a first voltage controlled oscillator output from the plurality of voltage controlled oscillator outputs to a second voltage controlled oscillator output from the plurality of voltage controlled oscillator outputs in a counter-clockwise manner. 
 
     
     
       44. The method of  claim 39 , wherein the step of generating the divided feedback signal comprises:
 incrementally switching from a first voltage controlled oscillator output from the plurality of voltage controlled oscillator outputs to a second voltage controlled oscillator output from the plurality of voltage controlled oscillator outputs in a clockwise manner. 
 
     
     
       45. The method of  claim 39 , wherein the step of generating the divided feedback signal comprises:
 switching from a first voltage controlled oscillator output from the plurality of voltage controlled oscillator outputs to a second voltage controlled oscillator output from the plurality of voltage controlled oscillator outputs based on a falling edge of the first voltage controlled oscillator output. 
 
     
     
       46. The method of  claim 39 , wherein the step of generating the divided feedback signal comprises:
 switching from a first voltage controlled oscillator output from the plurality of voltage controlled oscillator outputs to a second voltage controlled oscillator output from the plurality of voltage controlled oscillator outputs based on a rising edge of the first voltage controlled oscillator output. 
 
     
     
       47. A phase-locked loop (PLL), configured to receive a reference signal, comprising:
 a phase detector configured to output an error signal based on a difference between a divided feedback signal and the reference signal; 
 a voltage controlled oscillator configured to output a plurality of voltage controlled oscillator outputs based on the error signal; and 
 a fractional frequency divider configured to select among one or more pairs of voltage controlled oscillator outputs from the plurality of voltage controlled oscillator outputs to generate the divided feedback signal, each pair of voltage controlled oscillator outputs including a first voltage controlled oscillator output and a second voltage controlled oscillator output. 
 
     
     
       48. The PLL of  claim 47 , wherein the first voltage controlled oscillator output is substantially offset in phase by π from the second voltage controlled oscillator output.