Method and apparatus for encoding and decoding data

Abstract

A method and apparatus for encoding and decoding data is provided herein. During operation, A structured parity-check matrix H is provided to the encoder and decoder, where H is an m by n matrix and an expansion of a model matrix H bm of size m b by n b , where m=m b ×z and n=n b ×z. For a given code rate, multiple code sizes are accommodated by allowing both the model matrix size n b and the expansion factor z to vary.

1. A method for operating a transmitter that generates parity-check bits p=(p 0 , . . . , p m-1 ) based on an information block s=(s 0 , . . . , s k-1 ), the method comprising the steps of:
 receiving the information block s=(s 0 , . . . , s k-1 ); 
 using a matrix H to determine the parity-check bits; and 
 transmitting the parity-check bits along with the information block; 
 wherein H is an m by n matrix and an expansion of a model matrix H bm  of size m b  by n b  and wherein m=m b ×z and n=n b ×z, and wherein model matrix size n b  varies and expansion factor z varies for a given code rate, 1≦z≦z 0 , to provide H matrices of different sizes. 
 
     
     
       2. The method of  claim 1  wherein the expansion factor z is a factor of z 0 . 
     
     
       3. The method of  claim 1  wherein n b  is a value taken from a set of possible values for n b  and z is a value taken from a set of possible values of z. 
     
     
       4. The method of  claim 1  wherein expansion factor z varies with code size n. 
     
     
       5. The method of  claim 1  wherein model matrix size n b  varies with code size n. 
     
     
       6. The method of  claim 1  wherein a model matrix H bm  is derived from a mother model matrix by scaling operations. 
     
     
       7. The method of  claim 1  wherein a model matrix H bm  is derived from a mother model matrix by modulo operations. 
     
     
       8. The method of  claim 1  wherein matrix H is used to obtain a second H matrix via shortening and/or puncturing. 
     
     
       9. The method of  claim 1  wherein the encoder/decoder performs cyclic shifting for multiple vector sizes using the cyclic shift circuitry of a single vector length. 
     
     
       10. A method for estimating an information block s=(s 0 , . . . , s k-1 ), the method comprising the steps of:
 receiving a signal vector y=(y 0 , . . . , y n-1 ); and 
 using a matrix H to estimate the information block (s 0 , . . . , s k-1 ); 
 wherein H is an m by n matrix and an expansion of a model matrix H bm  of size m b  by n b  and wherein m=m b ×z and n=n b ×z, and wherein model matrix size n b  varies and expansion factor z varies for a given code rate, 1≦z≦z 0 , to provide H matrices of different sizes. 
 
     
     
       11. The method of  claim 10  wherein the expansion factor z is a factor of z 0 . 
     
     
       12. The method of  claim 10  wherein n b  is a value taken from a set of possible values for n b  and z is a value taken from a set of possible values of z. 
     
     
       13. The method of  claim 10  wherein expansion factor z varies with code size n. 
     
     
       14. The method of  claim 10  wherein model matrix size n b  varies with code size n. 
     
     
       15. The method of  claim 10  wherein a model matrix H bm  is derived from a mother model matrix by scaling operations. 
     
     
       16. The method of  claim 10  wherein a model matrix H bm  is derived from a mother model matrix by modulo operations. 
     
     
       17. The method of  claim 10  wherein matrix H is used to obtain a second H matrix via shortening and/or puncturing. 
     
     
       18. The method of  claim 10  wherein the encoder/decoder performs cyclic shifting for multiple vector sizes using the cyclic shift circuitry of a single vector length. 
     
     
       19. An apparatus comprising:
 logic circuitry receiving an information block s=(s 0 , . . . , s k-1 ) and using a matrix H to determine parity-check bits, wherein H is an m by n matrix and an expansion of a model matrix H bm  of size m b  by n b  and wherein m=m b ×z and n=n b ×z, and wherein model matrix size n b  varies and expansion factor z varies for a given code rate, 1≦z≦z 0 , to provide H matrices of different sizes; and 
 a transmitter transmitting the parity-check bits along with the information block. 
 
     
     
       20. An apparatus comprising:
 a receiver receiving a signal vector y=(y 0 , . . . , y n-1 ); and 
 logic circuitry using a matrix H to estimate an information block (s 0 , . . . , s k-1 ), wherein H is an m by n matrix and an expansion of a model matrix H bm  of size m b  by n b  and wherein m=m b ×z and n=n b ×z, and wherein model matrix size n b  varies and expansion factor z varies for a given code rate, 1≦z≦z 0 , to provide H matrices of different sizes.