Semiconductor memory device having faulty cells

Abstract

In response to a read command received by a system interface unit for accessing a plurality of blocks of data stored in said non-volatile semiconductor memory, a controller carries out selective read operations of blocks of data to two memories from the non-volatile semiconductor memory. The controller also carries out parallel operations of data transferring a first block of data, which has already been subjected to error detection and error correction operations by an error correction unit, from one of the two memories to a host system via said system interface unit and of data transferring of a second block of data to be subjected to the error detection and error correction operation, from said non-volatile semiconductor memory to the other of the two memories.

What we claim is: 
     
       1. A nonvolatile memory apparatus comprising:
 a control unit; 
 a main storage medium of the apparatus including an electrically reloadable nonvolatile memory having a plurality of memory cells, 
 wherein the electrically reloadable nonvolatile memory is adapted to be operable even when faulty memory cells exist therein; and 
 faulty registration means including a reloadable memory for registering address values of faulty regions of the main storage medium containing therein the faulty memory cells, 
 wherein data which is stored in the electrically reloadable nonvolatile memory is divided into blocks, each block having a plurality of data to be administrated and which is assigned an access address by the control unit, an administrative information region being provided in each block, and 
 wherein the control unit is adapted to carry out (i) access requests of the main storage medium and (ii) administration of faulty regions and a number of reloading occurrences of reloading of respective ones of the memory cells of the electrically reloadable nonvolatile memory in the main storage medium. 
 
     
     
       2. A nonvolatile memory apparatus comprising according to  claim 1 ,
 wherein, when the control unit detects a faulty memory cell associated with a respective block, the control unit is adapted to enter an access address of that block including the faulty memory cell as a registered address value in the reloadable memory of the faulty registration means, and 
 wherein, when the control unit receives an access request, the control unit decodes contents of the access request transmitted thereto to calculate an address of the data which has been transmitted thereto together with the access request and then recognizes an address value obtained as an administrative address, the control unit then ascertains from the faulty registration means whether or not an access value is associated with a faulty memory cell in the main storage medium and if it is determined to be a faulty memory cell, a replacement address value with which the address value of the faulty memory cell is to be replaced is designated in the faulty registration means. 
 
     
     
       3. A nonvolatile memory apparatus comprising according to  claim 2 ,
 wherein the reloadable memory of the faulty registration means includes a dynamic random access memory (DRAM) or a static random access memory (SRAM). 
 
     
     
       4. A nonvolatile memory apparatus comprising according to  claim 1 ,
 wherein the reloadable memory of the faulty registration means includes a dynamic random access memory (DRAM) or a static random access memory (SRAM). 
 
     
     
       5. A nonvolatile memory apparatus comprising according to  claim 1 ,
 wherein the electrically reloadable nonvolatile memory contains one or more flash memory chips. 
 
     
     
       6. A nonvolatile memory apparatus comprising according to  claim 5 ,
 wherein the reloadable memory of the faulty registration means includes a dynamic random access memory (DRAM) or a static random access memory (SRAM).