Method of fabricating an integrated circuit

Abstract

Methods of fabricating an integrated circuit, in particular a dynamic random access memory are described. After forming memory cells on a semiconductor substrate a mirror layer is provided, said mirror layer covering the memory cells. Then logic devices are formed adjoining to said memory cells covered by said mirror layer, said forming of said logic devices including activating the dopants in dopant regions by means of a radiation annealing, said radiation being reflected by said mirror layer. After at least partly removing the mirror layer; a wiring of the memory cells and of the logic devices is formed.

1. A method of fabricating an integrated circuit including the steps of:
 providing a semiconductor substrate; 
 processing the semiconductor substrate to form first devices; 
 providing a mirror layer on the semiconductor substrate, the mirror layer covering the first devices; 
 processing the semiconductor substrate to form second devices adjoining to said first devices covered by said mirror layer, said forming of the second devices including a radiation annealing, said radiation being reflected at least partly by said mirror layer; 
 at least partly removing the mirror layer; and 
 processing of the semiconductor substrate to form a wiring of the first devices and of the second devices. 
 
     
     
       2. The method of  claim 1 , wherein said mirror layer reflects at least 50% of said radiation. 
     
     
       3. The method of  claim 1 , wherein said mirror layer is a metal layer. 
     
     
       4. The method of  claim 1 , wherein said mirror layer forms an extended cover of said first devices, said mirror layer projecting at least 100 nm beyond said first devices. 
     
     
       5. A method of fabricating an integrated circuit including the steps of:
 providing a semiconductor substrate; 
 processing the semiconductor substrate to form memory cells; 
 providing a mirror layer on the semiconductor substrate, the mirror layer covering the memory cells; 
 processing the semiconductor substrate to form logic devices adjoining to said memory cells covered by said mirror layer, said forming of the logic devices including activating the dopants in dopant regions by means of a radiation annealing, said radiation being reflected at least partly by said mirror layer; 
 partly removing the mirror layer; and 
 processing of the semiconductor substrate to form a wiring of the memory cells and of the logic devices, said remaining parts of the mirror layer being parts of the wiring of the memory cells. 
 
     
     
       6. The method of  claim 5 , wherein said mirror layer reflects at least 50% of said radiation. 
     
     
       7. The method of  claim 5 , wherein said mirror layer is a metal layer. 
     
     
       8. The method of  claim 5 , wherein said mirror layer forms an extended cover of said memory cells, said mirror layer projecting at least 100 nm beyond said memory cells. 
     
     
       9. A method of fabricating an integrated circuit including the steps of:
 providing a semiconductor substrate; 
 processing of the semiconductor substrate to form a dynamic memory cell array including a plurality of memory cells, each memory cell having a storage capacitor and an access transistor with two source/drain regions and a gate region; 
 retention annealing of the semiconductor memory cells; 
 providing a mirror layer on the semiconductor substrate, the mirror layer covering the memory cell array; 
 processing the semiconductor substrate to form logic transistor devices adjoining to said memory cells covered by said mirror layer, said forming of the logic transistor devices including activating the dopants in dopant regions by means of laser annealing or flash annealing, said radiation being reflected at least partly by said mirror layer; 
 at least partly removing the mirror layer; and 
 processing the semiconductor substrate to form a wiring of the memory cells and of the logic transistor devices. 
 
     
     
       10. The method of  claim 9 , wherein said mirror layer reflects at least 50% of said radiation. 
     
     
       11. The method of  claim 9 , wherein said mirror layer forms an extended cover of said dynamic memory cell array, said mirror layer projecting at least 100 nm beyond said dynamic memory cell array. 
     
     
       12. A method of fabricating an integrated circuit including the steps of:
 providing a semiconductor substrate; 
 processing of the semiconductor substrate to form a dynamic memory cell array including a plurality of memory cells, each memory cell having a storage capacitor and an access transistor with two source/drain regions and a gate region; 
 retention annealing of the semiconductor memory cells; 
 providing a metal layer on the semiconductor substrate, the metal layer covering the memory cell array and electrically contacting one of the source/drain regions of the transistors; 
 processing the semiconductor substrate to form logic transistor devices adjoining to said memory cells covered by said metal layer, said forming of the logic transistor devices including forming dopant regions, and activating the dopants in the dopant regions by means of laser annealing or flash annealing; 
 partly removing the metal layer, said remaining parts of the metal layer are contacts to the one source/drain regions of the access transistors; and 
 processing the semiconductor substrate to form a wiring of the memory cells and of the logic transistor devices, said contacts being part of the wiring of the memory cells. 
 
     
     
       13. The method of  claim 12 , wherein said metal layer reflects at least 50% of said radiation. 
     
     
       14. The method of  claim 12 , wherein said metal layer forms an extended cover of said dynamic memory cell array, said metal layer projecting at least 100 nm beyond said dynamic memory cell array. 
     
     
       15. Method of  claim 12 , wherein the metal layer comprises tungsten.