Method of creating a netlist for an FPGA and an ASIC

Abstract

A method for developing integrated circuits includes generating a core (logic core) in an HDL format readable by a logic synthesis tool, from an ASIC core (logic core) made of ports of blocks and port connection information, creating a temporary chip design from chip terminal information to generate a terminal in the temporary chip design, generating a design identical to that created, as a cell within the design created, connecting a design port with a cell port, wherein a name of the design port is identical to a name of the cell port, inserting an I/O buffer, depending on the device technology, into a net between the ports connected, replacing the cell by the core (logic core) created to gerate a netlist, and expanding a hierarchy of the design, being the top hierarchy.

The invention claimed is: 
     
       1. A computer-implemented method of creating a netlist for an FPGA and an ASIC, comprising:
 on the one hand, when concurrent development of the FPGA and the ASIC is conducted, creating, by using a computer, FPGA design information in which identical terminals in a first design and a second design are connected, and a buffer corresponding to a device technology of the FPGA is inserted between the terminals, from the first design and the second design, wherein terminal information of the FPGA including whole or a part of functional blocks of a plurality of functional blocks is described in the first design, and the terminal information identical to that of the FPGA described as a low-order layer of a hierarchical design layer of the first design is described in the second design; 
 on the other hand, when concurrent development of the FPGA and the ASIC is conducted, creating ASIC design information in which identical terminals in a third design and a fourth design are connected, and a buffer corresponding to a device technology of the ASIC is inserted between the terminals, from the third design and the fourth design, wherein terminal information of the ASIC including the functional blocks is described in the third design, and the terminal information identical to that of the ASIC described as a low-order layer of a hierarchical design layer of the third design is described in the fourth design; and 
 creating the netlist for the FPGA and the ASIC by replacing the second design by the FPGA design information created and the fourth design by the ASIC design information created, based on connection information of functional blocks included in each of the second design and the fourth design.