Clock recovering circuit utilizing a delay locked loop for generating an output clock locked to an analog input signal and related method thereof

Abstract

A clock recovering circuit for generating an output clock locked to an analog input signal includes: a phase detection unit for receiving the analog input signal and the feedback clock for generating a phase error signal according to the analog input signal and the feedback clock; a loop filter coupled to the phase detector for filtering the phase error signal and generating a control signal; a numerically controlled oscillator (NCO) coupled to the loop filter for generating a first clock and an index signal according to the control signal; a delay locked loop (DLL) coupled to the NCO for receiving the first clock and generating a plurality of second clocks; and a multiplexer coupled to the NCO and the DLL for selecting one of the second clocks as the output clock according to the index signal.

1. A clock recovering circuit for generating an output clock that is locked to an analog input signal, comprising:
 a phase detection unit for generating a phase error signal representing a phase error between the analog input signal and a feedback clock; 
 a loop filter coupled to the phase detector for filtering the phase error signal and generating a control signal; 
 a numerically controlled oscillator coupled to the loop filter for generating a first clock and an index signal according to the control signal, wherein the numerically controlled oscillator is clocked by a reference clock having a preset frequency; 
 a delay locked loop coupled to the numerically controlled oscillator for receiving the first clock and generating a plurality of second clocks; and 
 a multiplexer coupled to the numerically controlled oscillator and the delay locked loop for selecting one of the second clocks as the output clock according to the index signal; 
 wherein the feedback clock feeds back to the phase detection unit based on the output clock. 
 
     
     
       2. The clock recovering circuit of  claim 1 , wherein the clock recovering circuit further comprises: a divider for dividing the output clock to generate the feedback clock. 
     
     
       3. The clock recovering circuit of  claim 1 , wherein the clock recovering circuit further comprises: a multiplier for multiplying the output clock to generate the feedback clock. 
     
     
       4. The clock recovering circuit of  claim 1 , wherein the phase detection unit comprises:
 an analog-to-digital converter for converting the analog input signal to a digital input signal wherein the analog-to-digital converter is clocked by the feedback clock; and 
 a first phase detector coupled to the analog-to-digital converter for generating a phase error signal according to the digital input signal. 
 
     
     
       5. The clock recovering circuit of  claim 1 , wherein the phase detection unit comprises:
 a slicer for slicing the analog input signal to a sliced input signal; and 
 a second phase detector for generating a phase error signal according to the sliced input signal and the feedback clock. 
 
     
     
       6. The clock recovering circuit of  claim 1 , wherein the loop filter, and the multiplexer are clocked by the first clock. 
     
     
       7. The clock recovering circuit of  claim 1 , wherein the loop filter is clocked by the first clock and the multiplexer is clocked by the output clock. 
     
     
       8. The clock recovering circuit of  claim 1 , wherein the edges of the plurality of second clocks output from the delay locked loop are substantially evenly spaced within one period of the reference clock. 
     
     
       9. The clock recovering circuit of  claim 1 , wherein the delay locked loop is an analog delay locked loop. 
     
     
       10. The clock recovering circuit of  claim 1 , wherein the delay locked loop is a digital delay locked loop. 
     
     
       11. The clock recovering circuit of  claim 1 , wherein the loop filter is a proportional-integral filter. 
     
     
       12. The clock recovering circuit of  claim 1 , wherein the analog input signal is an EFM (Eight-to-Fourteen Modulation) signal. 
     
     
       13. A method for generating an output clock that is locked to an analog input signal comprising:
 (a) generating a phase error signal representing a phase error between the analog input signal and a feedback clock; 
 (b) filtering the phase error signal and generating a control signal; 
 (c) generating a first clock and an index signal by feeding the control signal to a numerically controlled oscillator, which is clocked by a reference clock having a preset frequency; 
 (d) providing a delay locked loop, and utilizing the delay locked loop for receiving the first clock and generating a plurality of second clocks; 
 (e) selecting one of the second clocks as the output clock according to the index signal; and 
 (f) providing the feedback clock based on the output clock. 
 
     
     
       14. The method of  claim 13 , wherein the step (f) comprises dividing the output clock to generate the feedback clock. 
     
     
       15. The method of  claim 13 , wherein the step (f) comprises multiplying the output clock to generate the feedback clock. 
     
     
       16. The method of  claim 13 , wherein the step (a) further comprises: converting the analog input signal to a digital input signal wherein the conversion is performed by an analog-to-digital converter clocked by the feedback clock; and generating a phase error signal according to the digital input signal. 
     
     
       17. The method of  claim 13 , wherein the step (a) further comprises: slicing the analog input signal to a sliced input signal; and generating a phase error signal according to the sliced input signal and the feedback clock. 
     
     
       18. The method of  claim 13 , wherein operation of steps (b) and (e) are clocked by the first clock. 
     
     
       19. The method of  claim 13 , wherein operation of step (b) is clocked by the first clock and operation of step (e) is clocked by the output clock. 
     
     
       20. The method of  claim 13 , wherein the edges of the plurality of second clocks are substantially evenly spaced within one period of the reference clock. 
     
     
       21. The method of  claim 13 , wherein the phase error signal comprises an integral error signal and a proportional error signal. 
     
     
       22. The method of  claim 21 , wherein the control signal comprises an integral control signal and a proportional control signal, and step (b) generates the integral control signal and the proportional control signal by feeding the integral error signal and the proportional error signal to a proportional-integral filtering. 
     
     
       23. The method of  claim 13 , wherein the analog input signal is an EFM signal.