Prefetch miss indicator for cache coherence directory misses on external caches

Abstract

A system, method and article of manufacture for reducing latencies associated with cache coherence directory misses on external caches in a shared distributed memory data processing system. A cache coherence directory is evaluated for possible prefetching of a directory entry into a directory cache. A prefetch miss indicator is set if the prefetch evaluated results in a directory miss. The prefetch miss indicator is consulted during subsequent processing of a memory block request corresponding to the directory entry. An accelerated snoop response action is taken if the prefetch miss indicator is set. The latency of a second lookup into the cache coherence directory, which would otherwise be required, is thereby avoided.

1. A directory-based cache coherence controller system for reducing latency associated with cache coherence directory misses on external caches in a shared distributed memory data processing system, comprising:
 a cache coherence directory; 
 a directory cache; 
 first caching logic for evaluating said cache coherence directory for possible presetting of a directory entry into said directory cache; 
 second caching logic for setting a prefetch miss indicator in response to said prefetch evaluation resulting in a directory miss; 
 first protocol logic for consulting said prefetch miss indicator during subsequent processing of a memory request corresponding to said directory entry; and 
 second protocol logic for taking an accelerated snoop response action without reevaluating said directory based on said prefetch miss indicator being set. 
 
     
     
       2. The system of  claim 1  wherein said cache coherence directory is a full mapped directory. 
     
     
       3. The system of  claim 1  wherein said cache coherence directory is a sparse directory. 
     
     
       4. The system of  claim 1  wherein said second caching logic includes logic for storing a tag for said directory entry. 
     
     
       5. The system of  claim 1  further including a prefetch miss buffer and wherein said second caching logic includes logic for storing a tag for said directory entry in a prefetch miss buffer. 
     
     
       6. The system of  claim 5  wherein said prefetch miss buffer comprises an addressable memory. 
     
     
       7. The system of  claim 5  wherein said prefetch miss buffer comprises a storage register. 
     
     
       8. The system of  claim 1  wherein said second caching logic includes logic for setting a prefetch miss status indicator in said directory entry and storing said entry in said directory cache. 
     
     
       9. The system of  claim 1  wherein said first protocol logic includes logic for consulting a prefetch miss buffer in conjunction with consulting said directory cache. 
     
     
       10. The system of  claim 1  wherein said first protocol logic includes logic for consulting said directory cache to identify a directory entry having a prefetch miss status indicator. 
     
     
       11. A data processing node adapted for network interconnection in a shared distributed memory data processing system, comprising:
 a plurality of processors; 
 a plurality of caches respectively associated with said processors; 
 a node main memory; 
 a coherence controller; 
 a bus interconnecting said caches, said main memory and said coherence controller; 
 a cache coherence directory for locating cached copies of local memory blocks in external nodes of said data processing system; 
 a directory cache for temporarily storing directory entries from said cache coherence directory; 
 first caching logic in said coherence controller for evaluating said cache coherence directory for possible prefetching of a directory entry into said directory cache; 
 second caching logic in said coherence controller for setting a prefetch miss indicator as a result of said prefetch evaluation resulting in a directory miss signifying that there are no external cached copies of a memory block associated with said directory entry; 
 first protocol logic for consulting said prefetch miss indicator during subsequent processing of a memory block request corresponding to said directory entry; and 
 second protocol logic for taking an accelerated snoop response action without reevaluating said directory based on said prefetch miss indicator being set; 
 whereby latency associated with said directory miss is reduced by virtue of said accelerated response. 
 
     
     
       12. An article of manufacture for reducing latency associated with cache coherence directory misses on external caches in a shared distributed memory data processing system, comprising:
 one or more data storage media; 
 means recorded on said data storage media for programming a device to operate as by: 
 evaluating a cache coherence directory for possible prefetching of a directory entry into a directory cache; 
 setting a prefetch miss indicator in response to said prefetch evaluation resulting in a directory miss; 
 consulting said prefetch miss indicator during subsequent processing of a memory request corresponding to said directory entry; and 
 taking an accelerated snoop response action without reevaluating said directory based on said prefetch miss indicator being set. 
 
     
     
       13. The article of  claim 12  wherein said directory evaluating includes evaluating a full mapped directory. 
     
     
       14. The article of  claim 12  wherein said directory evaluating includes evaluating a sparse directory. 
     
     
       15. The article of  claim 12  wherein said setting of a prefetch miss indicator includes storing a tag for said directory entry. 
     
     
       16. The article of  claim 12  wherein said setting of a prefetch miss indicator includes storing a tag for said directory entry in a prefetch miss buffer. 
     
     
       17. The article of  claim 12  wherein said prefetch miss buffer comprises an addressable memory. 
     
     
       18. The article of  claim 12  wherein said prefetch miss buffer comprises a storage register. 
     
     
       19. The article of  claim 12  wherein said setting of a prefetch miss indicator includes setting a prefetch miss status indicator in said directory entry and storing said entry in said directory cache. 
     
     
       20. The article of  claim 12  wherein said consulting of said prefetch miss indicator is performed by consulting a prefetch miss buffer in conjunction with consulting said directory cache. 
     
     
       21. The article of  claim 12  wherein said consulting of said prefetch miss indicator is performed by consulting said directory cache to identify a directory entry having a prefetch miss status indicator.