Memory cell dual pocket implant

Abstract

A method of forming implants for a memory cell includes forming an oxide-nitride-oxide (ONO) stack over a substrate and implanting first impurities in the substrate adjacent each side of the ONO stack using a first implantation energy and a first tilt angle to produce first pocket implants. The method further includes implanting second impurities in the substrate adjacent each side of the ONO stack using a second implantation energy and a second tilt angle to produce second pocket implants, where the second implantation energy is substantially larger than the first implantation energy and where the second tilt angle is substantially larger than the first tilt angle.

1. A method of forming implants for a memory cell, comprising:
 forming an oxide-nitride-oxide (ONO) stack over a substrate; 
 implanting first p-type impurities in the substrate adjacent each side of the ONO stack at a dosage of about 5E13 atoms/cm 2  to about 1E15 atoms/cm 2 , at an implantation energy of about 2 KeV to about 5 KeV, and at a tilt angle of approximately 0 degrees to approximately 5 degrees relative to an upper surface of the substrate, wherein the first p-type impurities control program and erase speed for the memory cell; and 
 implanting second p-type impurities in the substrate adjacent each side of the ONO stack at a dosage of about 1E13 atoms/cm 2  to about 1E14 atoms/cm 2 , at an implantation energy of about 7 KeV to about 20 KeV, and at a tilt angle of approximately 35 degrees to approximately 55 degrees relative to an upper surface of the substrate, wherein the second p-type impurities control a threshold voltage (V T ) for the memory cell. 
 
   
   
     2. The method of  claim 1 , wherein the first p-type impurities comprise one of boron, BF 2 , or indium. 
   
   
     3. The method of  claim 1 , wherein the second p-type impurities comprise one of boron, BF 2 , or indium. 
   
   
     4. A method of forming a memory cell, comprising:
 forming a column over a substrate, the column comprising a first oxide layer, a charge storage layer and a second oxide layer; 
 forming a bit line in the substrate adjacent a side of the column; 
 implanting a first pocket of p-type impurities through the bit line adjacent the side of the column using a low implantation energy and a small tilt angle, wherein implanting the first pocket of impurities comprises implanting the first pocket of impurities at a dosage of about 1E14 atoms/cm 2  to about 1E15 atoms/cm 2  and at an implantation energy of about 2 KeV to about 5 KeV; and 
 implanting a second pocket of p-type impurities through the bit line adjacent the side of the column using a high implantation energy and a large tilt angle, wherein implanting the second pocket of impurities comprises implanting the second pocket of impurities at a dosage of about 1E13 atoms/cm 2  to about 1E14 atoms/cm 2  and at an implantation energy of about 7 KeV to about 20 KeV, 
 wherein implanting the first pocket of p-type impurities and implanting the second pocket of p-type impurities permits independent control of a voltage threshold (V T ) and program and erase speed for the memory cell. 
 
   
   
     5. The method of  claim 4 , wherein implanting the first p-type pocket of impurities comprises:
 implanting the first pocket of impurities at a tilt angle of approximately 0 degrees to approximately 5 degrees. 
 
   
   
     6. The method of  claim 4  wherein the first pocket of p-type impurities comprises one of boron, BF 2 , or indium. 
   
   
     7. The method of  claim 4 , wherein implanting the second pocket of p-type impurities comprises:
 implanting the second pocket of p-type impurities at a tilt angle of approximately 35 degrees to approximately 55 degrees. 
 
   
   
     8. The method of  claim 4 , wherein the second pocket of p-type impurities comprises one of boron, BF 2 , or indium. 
   
   
     9. The method of  claim 4 , wherein forming the bit line comprises:
 implanting impurities at a dosage of about 5E14 atoms/cm 2  to about 5E15 atoms/cm 2  and at an implantation energy of about 3 KeV to about 15 KeV. 
 
   
   
     10. The method of  claim 9 , wherein forming the bit line comprises:
 implanting the impurities at a tilt angle of approximately 0 degrees. 
 
   
   
     11. The method of  claim 10 , wherein the impurities comprise one of arsenic or phosphorous.