P
US7685449B2ExpiredUtilityPatentIndex 83

Communication device, semiconductor integrated circuit device, and communication system

Assignee: MITSUMI ELECTRIC CO LTDPriority: Mar 13, 2006Filed: Mar 8, 2007Granted: Mar 23, 2010
Est. expiryMar 13, 2026(expired)· nominal 20-yr term from priority
Inventors:TERASAWA NAOYA
Y02D10/00H04L 25/028G06F 13/4291H04L 7/0004H04L 7/0008
83
PatentIndex Score
26
Cited by
8
References
8
Claims

Abstract

A disclosed communication device performs bidirectional serial communication by using a clock line and a data line. The communication device includes a starting condition detecting unit configured to detect a communication starting condition based on levels of the clock line and the data line and generate, in response to detecting the communication starting condition, a wake up signal for waking up another circuit in the communication device from a standby status; a clock sending/receiving unit connected to the clock line and configured to send/receive a clock signal; and an output control unit configured to fix the clock line at a predetermined level by using the clock sending/receiving unit so as to suspend the bidirectional serial communication after the wake up signal is received from the starting condition detecting unit and until a standby status cancel instruction indicating that the other circuit has woken up from the standby status is received from the other circuit. The bidirectional serial communication is performed with another communication device via the clock line and the data line after the other circuit has woken up.

Claims

exact text as granted — not AI-modified
1. A communication device for performing bidirectional serial communication by using a clock line and a data line, the communication device comprising:
 a starting condition detecting unit configured to detect a communication starting condition based on levels of the clock line and the data line and generate, in response to detecting the communication starting condition, a wake up signal for waking up another circuit in the communication device from a standby status; 
 a clock sending/receiving unit connected to the clock line and configured to send/receive a clock signal; and 
 an output control unit configured to fix the clock line at a predetermined level by using the clock sending/receiving unit so as to suspend the bidirectional serial communication after the wake up signal is received from the starting condition detecting unit and until a standby status cancel instruction indicating that the other circuit has woken up from the standby status is received from the other circuit; wherein 
 the bidirectional serial communication is performed with another communication device via the clock line and the data line after the other circuit has woken up. 
 
   
   
     2. The communication device according to  claim 1 , further comprising:
 an interface unit configured to convert a data signal received in series from the data line into parallel data by using the clock signal received from the clock line; and 
 an address match detecting unit configured to compare a destination address of the parallel data received from the interface unit with an address of the communication device and supply the parallel data to the other circuit if the destination address and the address match; wherein 
 the interface unit and the address match detecting unit enter the standby status together with the other circuit and wake up according to the wake up signal. 
 
   
   
     3. The communication device according to  claim 1 , wherein
 the starting condition detecting unit detects the communication starting condition when the clock line is in a high-level status and the data line is in a low-level status. 
 
   
   
     4. The communication device according to  claim 1 , wherein
 the other circuit enters the standby status when the bidirectional serial communication with the other communication device ends. 
 
   
   
     5. A semiconductor integrated circuit device, wherein
 the communication device according to  claim 1  is integrated in a semiconductor circuit. 
 
   
   
     6. The semiconductor integrated circuit device according to  claim 5 , wherein
 the other circuit calculates a residual battery energy quantity by integrating a charge current and a discharge current of a battery. 
 
   
   
     7. A battery pack in which the semiconductor integrated circuit device according to  claim 6  is installed together with the battery, wherein
 power is supplied from the battery to an electronic device, and 
 battery residual information is sent from the semiconductor integrated circuit device to the electronic device. 
 
   
   
     8. A communication system in which three or more of the communication devices according to  claim 1  are connected to the clock line and the data line.

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