High linearity charge pump method and apparatus

Abstract

A charge pump configured for use in a phase-locked loop includes positive and negative current sources, transistor switches, voltage nodes and one or more operational amplifiers, wherein the positive and negative current sources each includes an output node, the output nodes are respectively connected sequentially to the voltage nodes having substantially the same voltage, the transistor switches are configured to sequentially switch such that at all times there is one transistor switch connection, and the currents flows through the transistor switches into one of the voltage nodes. One of the voltage nodes is connected to the PLL filter and the transistor switches are connected to the PLL filter and are controlled by the phase error pulses. Two voltage nodes are possible. The second node provides feedback. The currents to the second node are supplied substantially simultaneously for the same amount of time.

1. A charge pump configured for use in a phase-locked loop (PLL), the charge pump comprising:
 a positive current source; 
 a negative current source; 
 a plurality of transistor switches; 
 a set of three voltage nodes; 
 and a plurality of operational amplifiers, wherein: 
 a) the positive and negative current sources each includes an output node; 
 b) the output nodes are respectively connected sequentially to the three voltage nodes having substantially the same voltage; 
 c) the transistor switches are configured to sequentially switch such that at all times there is one transistor switch connection; and 
 d) positive and negative currents from the positive and negative current sources, respectively, flow through the transistor switches into one of the three nodes; 
 wherein the PLL includes: 
 a) a phase detector configured to generate phase error pulses; and 
 b) a phase-locked loop (PLL) filter; 
 and wherein: 
 a) one of the three voltage nodes is connected to the PLL filter and the transistor switches are connected to the PLL filter and are controlled by the phase error pulses, 
 b) the second node is configured to generate a feedback voltage, which in combination with at least one of the operational amplifiers is configured to control matching of the positive and negative currents, and 
 c) the positive and negative currents are supplied to the second node substantially simultaneously for the same amount of time. 
 
     
     
       2. The charge pump of  claim 1 , wherein the third node is configured to absorb the positive and negative current during a time that the positive and negative currents are not supplied to the other first and second nodes, and the third node is configured to present the same voltage to the output nodes of the current sources. 
     
     
       3. The charge pump of  claim 2 , wherein the positive and negative currents are substantially matched. 
     
     
       4. The charge pump of  claim 3 , wherein the charge pump is configured to provide for low supply voltage operation and a fast power up of the charge pump. 
     
     
       5. The charge pump of  claim 2 , wherein a substantially constant voltage is placed on the outputs of the current sources in order to minimize potential charge injection during switching of the transistor switches. 
     
     
       6. A charge pump of a phase-locked loop comprising:
 a positive current source; 
 a negative current source; 
 a plurality of transistor switches; 
 a set of three voltage nodes; and 
 a plurality of operational amplifiers, wherein: 
 a) the positive and negative current sources each includes an output node, and the output nodes are respectively connected sequentially to the three voltage nodes having substantially the same voltage, 
 b) the transistor switches are configured to sequentially switch such that at all times there is one transistor switch connection, and 
 c) positive and negative currents from the positive and negative current sources, respectively, flow through the transistor switches into one of the three nodes; 
 a phase detector configured to generate phase error pulses; and 
 a phase-locked loop (PLL) filter, wherein: 
 a) one of the three voltage nodes is connected to the PLL filter and the transistor switches are connected to the PLL filter and are controlled by the phase error pulses; 
 b) the second node is configured to generate a feedback voltage which in conjunction with at least one of the operational amplifiers is configured to control matching of the positive and negative currents, and 
 c) the positive and negative currents are connected to the second node substantially simultaneously for the same amount of time. 
 
     
     
       7. The charge pump of  claim 6 , wherein the third node is configured to absorb the positive and negative current during a time that the positive and negative currents are not supplied to the other first and second nodes, and the third node is configured to present the same voltage to the output nodes of the current sources. 
     
     
       8. The charge pump of  claim 7 , wherein the positive and negative currents are substantially matched. 
     
     
       9. The charge pump of  claim 7 , wherein a substantially constant voltage is placed on the outputs of the current sources in order to minimize potential charge injection during switching of the transistor switches. 
     
     
       10. The charge pump of  claim 9 , wherein the charge pump is configured to provide for low supply voltage operation and a fast power up of the charge pump. 
     
     
       11. A charge pump configured for use in a phase-locked loop (PLL), the charge pump comprising:
 a positive current source; 
 a positive input node for receiving a positive control signal that controls the positive current source; 
 a negative current source; 
 a negative input node for receiving a negative control signal that controls the negative current source; 
 an output node of the charge pump, coupled to the positive current source and the negative current source to output a net positive or negative current based, at least in part, on the relative timing of the positive control signal and the negative control signal; 
 an operational amplifier having at least one input and at least two outputs, wherein one of the at least two outputs is used to control an on current level for the positive current source and another one of the at least two outputs is used to control an on current level for the negative current source and an input of the at least one input coupled to a node that provides an indication of a current imbalance, if any, between the positive current source and the negative current source; 
 a charge collector circuit coupled to a feedback node that collects positive current from the positive current source when a positive feedback signal is enabled and the positive control signal is not enabled and that collects negative current from the negative current source when a negative feedback signal is enabled and the negative control signal is not enabled. 
 
     
     
       12. The charge pump of  claim 11 , wherein the positive feedback signal and the negative feedback signal are enabled substantially simultaneously for the same amount of time. 
     
     
       13. The charge pump of  claim 11 , further comprising a third set of switches that draw current from the positive current source or provide current to the negative current source when the operational amplifier is not activated and the positive control signal is not enabled and the negative control signal is not enabled. 
     
     
       14. The charge pump of  claim 11 , wherein the charge collector circuit is a capacitor coupled between the feedback node and ground.