Input buffer circuit

Abstract

An input buffer circuit. In one embodiment, the input buffer circuit includes a first transistor operable to receive a first input signal, a second transistor operable to receive a second input signal, and a first mechanism coupled to the first transistor and to the second transistor. The first mechanism is operable to control the first and second transistors such that the first and second transistors can receive either single-ended input signals or differential input signals. According to the embodiments disclosed herein, the input buffer combines single-ended input and differential input functionalities without compromising performance.

1. A circuit comprising:
 an input buffer circuit comprising:
 a first transistor having a base that is operable to receive a first input signal; 
 a second transistor having a base that is operable to receive a second input signal, and wherein the second transistor has an emitter that is coupled directly to an emitter of the first transistor; and 
 a third transistor having a base that is coupled to a first reference voltage, wherein the third transistor has an emitter that is directly coupled to the emitter of the first transistor and directly coupled to the emitter of the second transistor, wherein the third transistor has a collector that is directly coupled to a collector of the second transistor, wherein the third transistor is operable to control the first and second transistors, wherein the third transistor enables both the first transistor and the second transistor to receive single-ended input signals and differential input signals, wherein, when operating in a single-ended input mode, the first transistor is operable to receive a single-ended input signal and the second transistor is turned off, and wherein, when operating in a differential input mode, both of the first and second transistors are operable to receive differential input signals and the third transistor is turned off. 
 
 
   
   
     2. The circuit of  claim 1  wherein the third transistor enables both the first transistor and the second transistor to receive single-ended input signals and differential input signals without a multiplexer. 
   
   
     3. The circuit of  claim 1  further comprising a fourth transistor and a fifth transistor that are operable to provide the first reference voltage, wherein the fourth and fifth transistors control a switching threshold voltage of the input buffer circuit. 
   
   
     4. The circuit of  claim 3  further comprising a sixth transistor operable to function as a balancing transistor, wherein the sixth transistor has an emitter that is coupled directly to the emitter of the first transistor and has a base that is coupled directly between the fourth and fifth transistors. 
   
   
     5. The circuit of  claim 3  further comprising a sixth transistor operable to function as a balancing transistor, wherein the sixth transistor remains off due to having a base that remains at a voltage level that is always lower that a voltage level at the base of the third transistor. 
   
   
     6. The circuit of  claim 3  further comprising a sixth transistor operable to function as a balancing transistor, wherein the sixth transistor has an emitter that is coupled directly to the emitter of the first transistor and has a base that is coupled directly between the fourth and fifth transistors, and wherein the sixth transistor remains off due to the base of the sixth transistor remaining at a voltage level that is always lower that a voltage level at the base of the third transistor. 
   
   
     7. The circuit of  claim 1  wherein the first and second transistors are operable to provide the input buffer circuit with compatibility to multiple input signal levels for different functions. 
   
   
     8. A circuit comprising:
 an input buffer circuit comprising:
 a first transistor having a base that is operable to receive a first input signal; 
 a second transistor having a base that is operable to receive a second input signal, and wherein the second transistor has an emitter that is coupled directly to an emitter of the first transistor; 
 a third transistor having a base that is coupled to a reference voltage, wherein the third transistor has an emitter that is directly coupled to the emitter of the first transistor and directly coupled to the emitter of the second transistor, wherein the third transistor has a collector that is directly coupled to a collector of the second transistor, wherein the third transistor is operable to control the first and second transistors, wherein the third transistor enables both the first transistor and the second transistor to receive single-ended input signals and differential input signals, wherein, when operating in a single-ended input mode, the first transistor is operable to receive a single-ended input signal and the second transistor is turned off, and wherein, when operating in a differential input mode, both of the first and second transistors are operable to receive differential input signals and the third transistor is turned off; and 
 a plurality of elements operable to provide the reference voltage, wherein the reference voltage controls a switching threshold voltage of the input buffer circuit. 
 
 
   
   
     9. The circuit of  claim 8  wherein the first and second transistors are operable to provide the input buffer circuit with compatibility to multiple input signal levels for different functions. 
   
   
     10. The circuit of  claim 8  further comprising a balancing transistor. 
   
   
     11. The circuit of  claim 10  wherein the balancing transistor remains off. 
   
   
     12. A circuit comprising:
 an input buffer circuit comprising:
 a first transistor having a base that is operable to receive a first input signal; 
 a second transistor having a base that is operable to receive a second input signal, and wherein the second transistor has an emitter that is coupled directly to an emitter of the first transistor; and 
 a third transistor having a base that is coupled to a reference voltage, wherein the third transistor has an emitter that is directly coupled to the emitter of the first transistor and directly coupled to the emitter of the second transistor, wherein the third transistor has a collector that is directly coupled to a collector of the second transistor, wherein the third transistor is operable to receive a reference voltage that controls the switching threshold voltage of the input buffer circuit based on whether the first and second transistors are receiving single-ended input signals or differential input signals, wherein the third transistor enables both the first transistor and the second transistor to receive single-ended input signals and differential input signals, wherein, when operating in a single-ended input mode, the first transistor is operable to receive a single-ended input signal and the second transistor is turned off, and wherein, when operating in a differential input mode, both of the first and second transistors are operable to receive differential input signals and the third transistor is turned off.