Charge coupled device with high quantum efficiency

Abstract

A six-phase charge coupled device (CCD) pixel includes a pixel pair, with each pixel having two adjacent control gates overlying corresponding variable potential wells, where voltages applied to the control gates enable charge to be accumulated into and transferred out of the wells. A clear window region overlies a fixed potential gradient region, decreasing in potential away from the control gates. This region enables a wide band of photons to be sensed by the photosensitive silicon of the CCD. The decreasing potential levels facilitate high charge transfer efficiency (i.e., high CTE) from pixel to pixel via the control or transfer gates. By applying particular voltages to the control gates, charge can be quickly and efficiently transferred between pixels. In addition, the window provides a self aligned mask for the implantation steps and thus prevents the formation of pockets (or wells) due to misalignments that decrease the charge transfer efficiency and causes non-uniformity problems as associated with prior art. Furthermore the window provides a flat region that can be covered with an anti-reflective (AR) coating layer, thus further increasing the quantum efficiency.

1. A method of operating a charge coupled device (CCD), comprising:
 applying a first voltage to a first control gate to create a first well underneath the first control gate and accumulate charge into the first well; 
 applying a second voltage to a second control gate to create a first barrier underneath the second control gate; 
 applying a third voltage to the second control gate to create a second well underneath the second control gate, wherein the first and second wells form a first combined well, and accumulate the charge into the first combined well underneath the first and second control gates; 
 applying a fourth voltage to the first control gate to create a second barrier underneath the first control gate and transfer the charge from the first well underneath the first control gate into the second well underneath the second control gate; and 
 applying a fifth voltage to the second control gate to create a third barrier underneath the second control gate to transfer the charge across a decreasing potential region underneath a first window region, wherein the decreasing potential region comprises a plurality of increasing doping concentrations. 
 
   
   
     2. The method of  claim 1 , further comprising applying a sixth voltage to a third control gate to create a third well underneath the third control gate and accumulate the charge from the decreasing potential region, wherein first, second, and third control gates are independently controlled. 
   
   
     3. The method of  claim 2 , further comprising applying a seventh voltage to a fourth control gate to create a fourth well underneath the fourth control gate, wherein the third and fourth wells form a second combined well, and accumulate the charge into the second combined well underneath the third and fourth control gates, wherein first, second, third, and fourth control gates are independently controlled. 
   
   
     4. The method of  claim 3 , further comprising applying an eighth voltage to the third control gate to create a fourth barrier underneath the third control gate and transfer the charge from the third well underneath the third control gate into the fourth well underneath the fourth control gate. 
   
   
     5. The method of  claim 4 , further comprising a ninth voltage to the fourth control gate to create a fifth barrier underneath the fourth control gate to transfer the charge across a decreasing potential region underneath a second window region. 
   
   
     6. The method of  claim 1 , wherein the first and third voltages are approximately equal and the second, fourth, and fifth voltages are approximately equal. 
   
   
     7. The method of  claim 1 , wherein the CCD is an N-channel device. 
   
   
     8. The method of  claim 7 , wherein the first and third voltages are positive voltages and the second, fourth, and fifth voltages are negative voltages. 
   
   
     9. The method of  claim 1 , wherein the CCD is a P-channel device. 
   
   
     10. The method of  claim 9 , wherein the first and third voltages are negative voltages and the second, fourth, and fifth voltages arc positive voltages. 
   
   
     11. The method of  claim 1 , wherein the decreasing potential region comprises non-stepwise gradual decreasing potential regions. 
   
   
     12. The method of  claim 1 , wherein the decreasing potential region comprises a plurality of stepwise decreasing potential regions. 
   
   
     13. The method of  claim 1 , wherein the first voltage is maintained at the first control gate when applying the second voltage to the second control gate. 
   
   
     14. A method of operating a charge coupled device (CCD), comprising:
 applying a first voltage to a first control gate to create a first well underneath the first control gate and accumulate charge into the first well; 
 applying a second voltage to a second control gate to create a first barrier underneath the second control gate; 
 applying a third voltage to the second control gate to create a second well underneath the second control gate, wherein the first and second wells form a first combined well, and accumulate the charge into the first combined well underneath the first and second control gates; 
 applying a fourth voltage to the first control gate to create a second barrier underneath the first control gate and transfer the charge from the first well underneath the first control gate into the second well underneath the second control gate; 
 applying a fifth voltage to the second control gate to create a third barrier underneath the second control gate to transfer the charge across a decreasing potential region underneath a first window region; 
 applying a sixth voltage to a third control gate to create a third well underneath the third control gate and accumulate the charge from the decreasing potential region, and 
 applying a seventh voltage to a fourth control gate to create a fourth well underneath the fourth control gate, wherein the third and fourth wells form a second combined well, and accumulate the charge into the second combined well underneath the third and fourth control gates, wherein the first, second, third, and fourth control gates are independently controlled. 
 
   
   
     15. The method of  claim 14 , further comprising applying an eighth voltage to the third control gate to create a fourth barrier underneath the third control gate and transfer the charge from the third well underneath the third control gate into the fourth well underneath the fourth control gate. 
   
   
     16. The method of  claim 15 , further comprising a ninth voltage to the fourth control gate to create a fifth barrier underneath the fourth control gate to transfer the charge across a decreasing potential region underneath a second window region. 
   
   
     17. The method of  claim 14 , wherein the first voltage is maintained at the first control gate when applying the second voltage to the second control gate.