Power control circuit, method of controlling power control circuit, and DLL circuit including power control circuit

Abstract

A power control circuit includes a check unit that receives a reference clock and generates a check signal for cyclically activating a feedback loop of a DLL circuit, a phase detecting unit that detects a phase difference between the reference clock and a feedback clock, and generates a phase difference detection signal, and a signal combining unit that generates a power cutoff signal in response to a locking completion signal, the check signal, and the phase difference detection signal.

1. A power control circuit, comprising:
 a check unit that receives a reference clock and generates a check signal using a control pulse signal which is toggled at every operation cycle of a DLL (Delay Locked Loop) circuit; 
 a phase detecting unit that detects a phase difference between the reference clock and a feedback clock, and generates a phase difference detection signal; and 
 a signal combining unit that generates a power cutoff signal for cutting a power supply to the DLL circuit in response to a locking completion signal, the check signal, and the phase difference detection signal. 
 
   
   
     2. The power control circuit of  claim 1 ,
 wherein the check unit repeatedly enables the check signal by a time corresponding to an operation cycle of the DLL circuit. 
 
   
   
     3. The power control circuit of  claim 1 ,
 wherein the check unit includes: 
 a control pulse generator that divides the reference clock by a predetermined ratio and generates the control pulse signal in a pulsed manner; and 
 a shift register that shifts a logic high level in response to the control pulse signal, a reset signal, and a first pulse signal, and generates the check signal. 
 
   
   
     4. The power control circuit of  claim 3 ,
 wherein the first pulse signal has a toggle timing more advanced than the toggle timing of the control pulse signal. 
 
   
   
     5. The power control circuit of  claim 3 ,
 wherein the shift register includes: 
 an initializer that receives a shift signal, the first pulse signal, and the reset signal, and generates an initialization signal; and 
 a shifter that is initialized in response to the initialization signal, and shifts the external power under the control of the control pulse signal to generate the shift signal and the check signal. 
 
   
   
     6. The power control circuit of  claim 5 ,
 wherein the initializer enables the initialization signal when the first pulse signal is toggled in a state where the check signal is enabled. 
 
   
   
     7. The power control circuit of  claim 1 ,
 wherein the phase detecting unit determines whether or not the phase difference between the reference clock and the feedback clock exceeds a predetermined range, 
 if the phase difference exceeds the predetermined range, enables the phase difference detection signal, and 
 if the phase difference is within the predetermined range, disables the phase difference detection signal. 
 
   
   
     8. The power control circuit of  claim 7 ,
 wherein the phase detecting unit includes: 
 a phase difference detector that detects the phase difference between the reference clock and the feedback clock, and generates a detection signal; and 
 a latch that latches and inverts the detection signal in response to a first pulse signal and generates the phase difference detection signal. 
 
   
   
     9. The power control circuit of  claim 8 ,
 wherein the phase difference detector includes: 
 a first detector that determines whether or not the feedback clock has a more advanced phase than the reference clock for a first time or more, and generates a first detection signal; 
 a second detector that determines whether or not the reference clock has a more advanced phase than the feedback clock for a second time or more, and generates a second detection signal; and 
 a combiner that combines the first detection signal and the second detection signal, and generates the detection signal. 
 
   
   
     10. A power control circuit, comprising:
 a check unit that receives a reference clock and generates a check signal for cyclically activating a feedback loop of a DLL (Delay Locked Loop) circuit; 
 a phase detecting unit that detects a phase difference between the reference clock and a feedback clock, and generates a phase difference detection signal; and 
 a signal combining unit that generates a power cutoff signal in response to a locking completion signal, the check signal, and the phase difference detection signal, 
 wherein the signal combining unit disables the power cutoff signal if the locking completion signal is disabled or if the phase difference detection signal or the check signal is enabled, and enables the power cutoff signal when the locking completion signal is enabled, and the phase difference detection signal and the check signal are disabled. 
 
   
   
     11. The power control circuit of  claim 10 ,
 wherein the signal combining unit includes: 
 a first combiner that combines the locking completion signal, the phase difference detection signal, and the check signal, and generates a combined signal; 
 a latch that latches the combined signal in response to a first pulse signal and outputs a latch signal; and 
 a second combiner that combines the combined signal and the latch signal, and outputs the power cutoff signal.