Pipelined converter systems with enhanced linearity

Abstract

Signal converter system embodiments are provided to substantially reduce symmetrical and asymmetrical conversion errors. Signal-processing stages of these embodiments may include a signal sampler in addition to successively-arranged signal converters. In system embodiments, injected analog dither signals are initiated in response to a random digital code. They combine with a system's analog input signal and the combined signal is processed down randomly-selected signal-processing paths of the converter system to thereby realize significant improvements in system linearity. Because these linearity improvements are realized by simultaneous processing of the input signal and the injected dither signal, a combined digital code is realized at the system's output. A first portion of this combined digital code corresponds to the analog input signal and a second portion corresponds to the injected analog dither signal. The final system digital code is realized by subtracting out the second portion with a back-end decoder that responds to the random digital code.

1. An analog-to-digital converter system to convert an analog input signal to a system digital code, comprising:
 a sampler to provide samples of said analog input signal; 
 signal converters arranged and configured to successively process said samples; 
 at least one digital-to-analog converter configured to respond to a random digital code and inject analog dither signals into at least a selected one of said sampler and said signal converters which process said samples and said analog dither signals into a plurality of digital codes; 
 an aligner/corrector coupled to said signal converters to process said plurality of digital codes into a combined digital code that includes a first portion that corresponds to said samples and a second portion that corresponds to said analog dither signals; and 
 a decoder having a transfer function configured to convert said random digital code to said second portion for differencing with said combined digital code to thereby provide said system digital code; 
 said samples thus processed along different signal-processing paths of said signal converters to thereby enhance linearity of said system. 
 
     
     
       2. The system of  claim 1 , further including:
 a pseudorandom generator to provide said random digital code; and 
 a differencer to difference said second portion and said combined digital code to provide said system digital code. 
 
     
     
       3. The system of  claim 1 , wherein said analog dither signals are injected into said sampler, an initial one of said signal converters is configured to provide analog output signals to a succeeding signal converter with an amplitude limited to an output-signal window, and the amplitude of said analog dither signals is selected so that said analog output signals dither over a predetermined dither range. 
     
     
       4. The system of  claim 3 , wherein said predetermined dither range is less than said output-signal window. 
     
     
       5. The system of  claim 3 , wherein said predetermined dither range is greater than said output-signal window. 
     
     
       6. The system of  claim 3 , wherein the amplitude of said analog dither signals is varied over N dither levels and said predetermined dither range is substantially (N−1)/N of said output-signal window. 
     
     
       7. The system of  claim 3 , wherein said sampler includes at least one capacitor and said digital-to-analog converter is configured to switchably couple different voltages to said capacitor to thereby inject said analog dither signals. 
     
     
       8. The system of  claim 1 , wherein:
 said analog dither signals are injected into a selected one of said signal converters which is configured to provide analog output signals to a succeeding signal converter with an amplitude limited to an output-signal window; and 
 the amplitude of said analog dither signals is selected so that said analog output signals dither over a predetermined dither range. 
 
     
     
       9. The system of  claim 8 , wherein said predetermined dither range is less than said output-signal window. 
     
     
       10. The system of  claim 8 , wherein said predetermined dither range is greater than said output-signal window. 
     
     
       11. The system of  claim 8 , wherein the amplitude of said analog dither signals is varied over N dither levels and said predetermined dither range is substantially (N−1)/N of said output-signal window. 
     
     
       12. The system of  claim 8 , wherein said selected signal converter includes at least first and second dither capacitors and said digital-to-analog converter is configured to switchably couple different voltages to said first dither capacitor to thereby contribute to said analog dither signals and switchably couple different voltages to said second dither capacitor to thereby contribute to a respective one of said plurality of digital codes. 
     
     
       13. An analog-to-digital converter system to convert an analog input signal to a system digital code, comprising:
 signal converters arranged and configured to provide and successively process samples of said analog input signal; 
 at least one digital-to-analog converter configured to respond to a random digital code and inject corresponding analog dither signals into at least a selected one of said signal converters to enable said selected signal converter and succeeding signal converters to successively process said analog dither signals, processing of said samples and said analog dither signals thereby generating a plurality of digital codes; 
 an aligner/corrector coupled to said signal converters to process said plurality of digital codes into a combined digital code that includes a first portion that corresponds to said samples and a second portion that corresponds to said analog dither signals; and 
 a decoder having a transfer function configured to convert said random digital code to said second portion for differencing with said combined digital code to thereby provide said system digital code; 
 said samples thus processed along different signal-processing paths of said signal converters to thereby enhance conversion linearity of said system. 
 
     
     
       14. The system of  claim 13 , further including:
 a pseudorandom generator to provide said random digital code; and 
 a differencer to difference said second portion and said combined digital code to provide said system digital code. 
 
     
     
       15. The system of  claim 13 , wherein:
 said selected signal converter is configured to provide analog output signals to a succeeding signal converter with an amplitude limited to an output-signal window; and 
 the amplitude of said analog dither signals is selected so that said analog output signals dither over a predetermined dither range. 
 
     
     
       16. The system of  claim 15 , wherein said predetermined dither range is less than said output-signal window. 
     
     
       17. The system of  claim 15 , wherein said predetermined dither range is greater than said output-signal window. 
     
     
       18. The system of  claim 15 , wherein the amplitude of said analog dither signals are varied over N dither levels and said predetermined dither range is substantially (N−1)/N of said output-signal window. 
     
     
       19. The system of  claim 15 , wherein said selected signal converter includes at least one dither capacitor and said digital-to-analog converter is configured to switchably couple different voltages to said dither capacitor to thereby contribute to said analog output signals. 
     
     
       20. The system of  claim 15 , wherein said selected signal converter includes at least one dither capacitor and said digital-to-analog converter is configured to switchably couple different voltages to said dither capacitor to thereby contribute to a respective one of said plurality of digital codes.