Storage device

Abstract

The object of the invention is to avoid an unselected data line being driven in a memory array composed of memory cells each of which uses a storage element depending upon variable resistance and a selection transistor when the selection transistors in all memory cells on a selected wordline conduct. To achieve the object, a source line parallel to a data line is provided, a precharge circuit for equipotentially driving both and a circuit for selectively driving the source line are arranged. Owing to this configuration, a current path is created in only a cell selected by a row decoder and a column decoder and a read-out signal can be generated. Therefore, a lower-power, lower-noise and more highly integrated nonvolatile memory such as a phase change memory can be realized, compared with a conventional type.

1. A storage device comprising:
 a first wiring layer formed above a substrate; 
 a second wiring layer formed above the first wiring layer; 
 a plurality of first lines formed in the first wiring layer; 
 a plurality of second lines formed in the second wiring layer; and 
 a plurality of memory cells formed between the first and second lines; 
 wherein each of the plurality of memory cells includes a storage element and a selection element, 
 wherein both of the storage element and the selection element in each of the memory cells are formed between a corresponding one of the first lines and a corresponding one of the second lines, 
 wherein a current flows in a direction perpendicular to the substrate through the selection element of each of the memory cells, 
 wherein a width, which is in a direction parallel to a surface of the substrate and parallel to an extending direction of the second lines, of the selection element is substantially the same as a width, which is in the direction parallel to the surface of the substrate and parallel to the extending direction of the second lines, of the storage element, 
 wherein the selection element includes polysilicon, and the storage element includes chalcogenide. 
 
     
     
       2. A storage device according to  claim 1 , wherein the second line is a bit line. 
     
     
       3. A storage device according to  claim 2 , wherein the first line and the second line are a metal line. 
     
     
       4. A storage device comprising:
 a first wiring layer formed above a substrate; 
 a second wiring layer formed above the first wiring layer; 
 a third wiring layer formed above the second wiring layer; 
 a fourth wiring layer formed above the third wiring layer; 
 a first line formed in the first wiring layer; 
 a second line formed in the second wiring layer and parallel to the first line; 
 a plurality of third lines formed in the third wiring layer, crossing to the first line and the second line; 
 a plurality of memory cells being arranged at the points of intersection of the plurality of third lines and the first line and comprising a storage element, the resistance of which varies according to stored information; 
 a first power supply line formed in the first wiring layer and supplying a first potential; 
 a second power supply line formed in the first wiring layer and supplying a second potential lower than the first potential; 
 a first common line formed in the first wiring layer and connected between the second line and a reading circuit or a writing circuit; 
 a first transistor formed on the substrate and connecting the first line and the first power supply line; 
 a second transistor formed on the substrate and connecting the second line and the first power supply line; 
 a third transistor formed on the substrate and connecting the first line and the second power supply line; 
 a fourth transistor formed on the substrate and connecting the second line and the first common line; and 
 a fourth line formed in the fourth wiring layer and connected to a gate of the third transistor and a gate of the fourth transistor. 
 
     
     
       5. A storage device according to  claim 4 ,
 wherein the plurality of memory cells comprising a first electrode formed on the first line, a channel layer formed on the first electrode, and a second electrode formed on the channel layer, and 
 wherein the storage element is formed on the second electrode and contacted with the second line. 
 
     
     
       6. A storage device according to  claim 5 ,
 wherein the plurality of third lines are provided to control the channel layer and are not electrically-connected to the first line and the second line. 
 
     
     
       7. A storage device according to  claim 6 ,
 wherein the channel layer is intrinsic polysilicon. 
 
     
     
       8. A storage device according to  claim 7 ,
 wherein the storage element includes chalcogenide. 
 
     
     
       9. A storage device according to  claim 8 ,
 wherein each of the first wiring layer, the second wiring layer and the fourth wiring layer is a metal layer. 
 
     
     
       10. A storage device according to  claim 1 , wherein the selection element flows said current therethrough by selecting a word line. 
     
     
       11. A storage device according to  claim 1 , wherein the selection element is a vertical transistor sandwiched between the first wiring layer and the second wiring layer, and the selection element has a source, a channel, and a drain stacked perpendicular to the substrate. 
     
     
       12. A storage device according to  claim 1 , wherein the memory element is stacked upon the selection element in a direction perpendicular to the substrate, and the elements are sandwiched between the first wiring layer and the second wiring layer. 
     
     
       13. A storage device according to  claim 1 , wherein the memory element is directly stacked upon the selection element in a direction perpendicular to the substrate, and the elements are directly sandwiched between the first wiring layer and the second wiring layer. 
     
     
       14. A storage device according to  claim 7 , wherein each of the first electrode and the second electrode is N-type polysilicon.