US7720077B1ActiveUtility

Timed packet processing to regulate data transfer between components of a gateway for a constant delay network

75
Assignee: CISCO TECH INCPriority: May 22, 2008Filed: May 22, 2008Granted: May 18, 2010
Est. expiryMay 22, 2028(~1.9 yrs left)· nominal 20-yr term from priority
H04L 47/10H04L 12/2801H04L 1/004H04J 3/0685
75
PatentIndex Score
8
Cited by
2
References
19
Claims

Abstract

In one embodiment, a gateway for a constant delay network identifies a baseband clock that is synchronized by exchanging synchronization messages over a packet switched network. The gateway then generates a strobe by manipulating the identified baseband clock using a custom multiplier that is selected according to transmission variables. The gateway then signals a front end component to process fixed length packets for transfer to a back end component according to the generated strobe, which can reduce or eliminate buffering by the back end component and can improve cable modem operation.

Claims

exact text as granted — not AI-modified
1. An apparatus for modulating received packet switched traffic for transfer over a constant transmission delay network, the apparatus comprising:
 a front end component to insert timestamps into headers of fixed length packets received over the packet switched network; 
 a back end component coupled to the front end component, the back end component to modulate data to be output onto the constant transmission delay network; and 
 a controller configured to: 
 identify a baseband clock that is synchronized according to synchronization messages exchanged between the apparatus and a remote network device over the packet switched network; 
 generate a strobe by adjusting the identified baseband clock; and 
 signal the front end component to timestamp the fixed length packets according to the generated strobe. 
 
   
   
     2. The apparatus of  claim 1  wherein the controller is further configured to:
 configure a symbol rate of the output modulated data; and 
 generate the strobe according to the configured symbol rate. 
 
   
   
     3. The apparatus of  claim 1  wherein the controller is further configured to:
 configure a symbol rate of the output modulated data and a modulation level for the output modulated data; 
 identify a reference data rate according to the configured symbol rate and modulation level; and 
 calculate a frequency of the strobe according to the identified reference data rate. 
 
   
   
     4. The apparatus of  claim 3  wherein the controller is further configured to:
 calculate the frequency by dividing the identified reference data rate lay a fixed length packet size of the fixed length packets; 
 select a custom clock multiplier that, when multiplied by the baseband clock, produces the calculated frequency; and 
 generate the strobe by multiplying the baseband clock by the selected custom clock multiplier. 
 
   
   
     5. The apparatus of  claim 1  wherein the identified baseband clock is a same clock used by the backend component during a modulation process. 
   
   
     6. The apparatus of  claim 1  wherein the back end component modulates the processed fixed length packets as they are received and without delay. 
   
   
     7. The apparatus of  claim 1  wherein the processed fixed length packets are transferred to the back end component without using a buffer. 
   
   
     8. The apparatus of  claim 1  wherein a first frequency of the strobe is greater than a second frequency of the identified baseband clock. 
   
   
     9. The apparatus of  claim 1  wherein the timestamps are inserted into the fixed length packets to replace timestamps inserted by a Data Over Cable Service Interface Specification (DOCSIS) Modular Cable Modem Termination System (M-CMTS) core. 
   
   
     10. An apparatus, comprising:
 means for obtaining a reference clock that is synchronized according to synchronization messages exchanged between the apparatus and a remote network device over a packet switched network; 
 means for generating a strobe by adjusting the reference clock; 
 means for controlling local timestamping of packets received over the packet switched network according to the generated strobe; 
 means for generating a modulated output signal that is based on the timestamped packets; and 
 means for adjusting the reference clock according to a symbol rate associated with the modulated output signal. 
 
   
   
     11. The apparatus of  claim 10  further comprising:
 means for identifying a modulation scheme and an error correction encoding scheme used to generate the modulated output signal; 
 means for selecting a custom clock multiplier according to the symbol rate, the modulation scheme, and the error correction encoding scheme; and 
 means for adjusting the reference clock using the selected custom clock multiplier. 
 
   
   
     12. The apparatus of  claim 10  wherein the generated strobe includes a pulse at every occurrence of a fixed interval, wherein no more than one of the timestamped packets is provided to modulation circuitry during each occurrence of the fixed interval. 
   
   
     13. The apparatus of  claim 10  wherein the timestamped packets are passed to modulation circuitry, and wherein a data rate for the timestamped packets is less than an output rate of the modulation circuitry. 
   
   
     14. A method, comprising:
 identifying a reference clock that is synchronized over a packet switched network; 
 generating a control signal by adjusting the identified reference clock; 
 controlling packet processing according to the generated control signal; 
 generating a modulated output signal that is based on the processed packets; and 
 adjusting the identified reference clock according to a symbol rate associated with the modulated output signal. 
 
   
   
     15. The method of  claim 14  wherein the generated control signal has a first frequency that is greater than a second frequency of a clock used for generating Data Over Cable Service Interface Specification (DOCSIS) timestamps. 
   
   
     16. The method of  claim 14  further comprising:
 identifying a modulation scheme and an error correction encoding scheme used to generate the modulated output signal; 
 selecting a custom clock multiplier according to the symbol rate, the modulation scheme, and the error correction encoding scheme; and 
 adjusting the identified reference clock using the selected custom clock multiplier. 
 
   
   
     17. The method of  claim 14  wherein the generated control signal includes a pulse at every occurrence of a fixed interval, wherein no more than one of the processed packets is passed to modulation circuitry during each occurrence of the fixed interval. 
   
   
     18. The method of  claim 14  wherein the processed packets are transferred to modulation circuitry, and wherein a data rate for the transferred packets corresponds to an output rate of the modulation circuitry. 
   
   
     19. The method of  claim 14  wherein the modulated output signal is encoded according to the J.83 specification.

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