Flash memory with recessed floating gate

Abstract

A flash memory device where the floating gate of the flash memory is defined by a recessed access device. The use of a recessed access device results in a longer channel length with less loss of device density. The floating gate can also be elevated above the substrate a selected amount so as to achieve a desirable coupling between the substrate, the floating gate and the control gate incorporating the flash cell.

1. A method of forming a flash memory device, the method comprising:
 forming an opening in a semiconductor substrate wherein the opening extends inward from a first surface of the semiconductor substrate; 
 forming a floating gate structure within the opening such that the floating gate structure has a portion recessed below a surface of the semiconductor substrate; 
 forming a control gate on the semiconductor substrate so as to be associated with the floating gate structure such that application of a first electrical signal between the control gate and the semiconductor substrate results in charge being stored in the floating gate structure which inhibits the formation of a conductive channel in the semiconductor substrate that is recessed below the surface of the semiconductor substrate and such that application of a second electrical signal between the control gate and the semiconductor substrate results in the removal of charge from the floating gate structure which thereby induces the formation of a conductive channel formed in the semiconductor substrate. 
 
   
   
     2. The method of  claim 1 , further comprising forming a pair of source/drain regions adjacent the floating gate structure such that the conductive channel interconnects the source/drain regions via a path that extends about the periphery of the floating gate structure formed in the semiconductor substrate. 
   
   
     3. A method of forming a memory device, the method comprising:
 forming an opening in a semiconductor substrate; 
 forming a floating gate structure at least partially within the opening, wherein the floating gate structure has a portion recessed below the surface of the semiconductor substrate; and 
 forming a control gate on the semiconductor substrate so as to be associated with the floating gate structure; 
 wherein the floating gate structure and the control gate are respectively contoured to achieve a selected level of capacitive coupling therebetween and wherein the control gate defines a recess and the floating gate structure is adapted to extend upwards from the surface of the semiconductor substrate by a selected distance and fit within the recess such that variation of the selected distance modifies the capacitive coupling between the floating gate structure, the semiconductor substrate, and the control gate to affect the ability of charge to be stored or removed from the floating gate structure. 
 
   
   
     4. The method of  claim 3 , wherein the control gate comprises a conductive member and an insulator that is interposed between the conductive member of the control gate and the floating gate structure. 
   
   
     5. The method of  claim 4 , wherein the insulator comprises oxynitride (ONO). 
   
   
     6. A method of forming a memory device, comprising:
 forming two source/drain regions which are coupled to a substrate, adjacent a surface of the substrate; 
 forming at least one recess access gate having a first portion which extends beneath the substrate surface into the substrate and a second portion which extends above the substrate surface by a selected distance and so as to be interposed between the two source/drain regions, wherein the at least one recessed access gate defines a conductive channel between the two source/drain regions that is recessed from the surface in the substrate and wherein the at least one recessed access gate has an upper surface proximate the surface of the substrate wherein the at least one recessed access gate defines at least one floating gate structure having an upper surface and wherein variation of the selected distance of the second portion of the recess access gate above the substrate modifies a capacitive coupling between the recess access gate, the substrate, and a control gate structure to thereby affect an ability of a charge to be stored or removed from the floating gate structure; and 
 forming at least one control gate structure on the upper surface of the at least one floating gate structure wherein the at least one control gate structure and the at least one floating gate structure are formed so as to allow charge to be selectively stored and removed from the at least one floating gate structure to selectively change a state of the conductive channel to thereby provide an indication of a memory state of the memory device. 
 
   
   
     7. The method of  claim 6 , wherein the at least one recessed access gate includes a conductive member and an insulator that is interposed between the conductive member and the substrate. 
   
   
     8. The method of  claim 7 , wherein the conductive member of the at least one recessed access device is formed of polysilicon and the insulator is formed of a high K dielectric material. 
   
   
     9. The method of  claim 6 , further comprising forming at least one select gate from at least one of the at least one recess access gate structures. 
   
   
     10. The method of  claim 8 , further comprising forming a select gate from at least one recess access gate structures, wherein the conductive members of a first plurality of recessed access gate structures are electrically interconnected to the control gate of a second plurality of recessed access gate structures. 
   
   
     11. The method of  claim 6 , further comprising forming isolation structures within the semiconductor substrate so as to isolate adjacent recessed access gate structures. 
   
   
     12. A method of forming a flash memory device, comprising:
 depositing an oxide layer over a semiconductor substrate; 
 depositing a nitride layer upon the oxide layer; 
 forming a recess within the oxide layer, the nitride layer, and the semiconductor substrate; 
 forming at least one recessed access gate structure within the recess, wherein the recessed access gate structure further defines a floating gate structure of the flash memory device; and 
 forming a control gate structure such that, when voltage is applied between the control gate structure and the semiconductor substrate, charge is stored in the floating gate structure, thereby creating a conductive channel in the semiconductor substrate and wherein upon removal of charge from the floating gate structure, the conducive channel in the semiconductor substrate is removed. 
 
   
   
     13. The method of  claim 12 , wherein the control gate structure comprises a first conductive layer which is isolated from the floating gate structure by a first insulating layer. 
   
   
     14. The method of  claim 12 , further comprising forming isolation structures within the semiconductor substrate so as to isolate adjacent recessed access gate structures. 
   
   
     15. The method of  claim 14 , wherein a plurality of openings are formed through the nitride layer, the oxide layer, the recessed access gate structures, and the semiconductor substrate and wherein the plurality of openings are filled with an oxide material. 
   
   
     16. The method of  claim 15 , wherein the isolation structures are recessed below an upper surface of the nitride layer and the upper surface of the recessed access gate. 
   
   
     17. The method of  claim 12 , further comprising removing the nitride layer and oxide layer surrounding the recessed access device so as to result in a portion of the at least one recessed access device extending upward above an upper surface of the semiconductor substrate so as to allow for greater capacitive coupling between the recessed access gate structure, the semiconductor substrate, and the control gate structure. 
   
   
     18. The method of  claim 13 , further comprising forming a select gate comprising the first insulating layer, a second conductive layer positioned upon the first insulating layer, a third conductive layer positioned upon the second conductive layer, and a second insulating layer positioned upon the third conductive layer. 
   
   
     19. A method of forming a flash memory device, comprising:
 forming a floating gate structure so as to extend into a semiconductor substrate, beneath a surface of the semiconductor substrate; and 
 forming a control gate structure adjacent to the surface of the semiconductor substrate so that application of a first voltage between the control gate structure and the semiconductor substrate results in charge being removed from the floating gate structure such that the floating gate structure defines a conductive path that is recessed in the semiconductor substrate about a periphery of the portion of the floating gate structure extending into the semiconductor substrate and so that application of a second voltage between the control gate structure and the semiconductor substrate results in charge being stored in the floating gate structure, changing the conductive channel formed in the semiconductor substrate. 
 
   
   
     20. The method of  claim 19 , wherein the floating gate structure comprises a recessed access gate transistor. 
   
   
     21. The method of  claim 20 , wherein the floating gate structure is capacitively coupled to the control gate and is capacitively coupled to the semiconductor substrate. 
   
   
     22. The method of  claim 21 , wherein the floating gate structure and the conductive gate structure are respectively contoured to achieve a selected level of capacitive coupling therebetween. 
   
   
     23. The method of  claim 22 , wherein the control gate structure defines a recess and the floating gate structure is adapted to extend upwards from the upper surface of the semiconductor substrate and to fit within the recess formed in the control gate structure such that an increased level of capacitive coupling proportionate to the first distance between the floating gate structure and the control gate structure occurs