P
US7723839B2ExpiredUtilityPatentIndex 95

Semiconductor device, stacked semiconductor device, and manufacturing method for semiconductor device

Assignee: SHARP KKPriority: Jun 10, 2005Filed: Jun 5, 2006Granted: May 25, 2010
Est. expiryJun 10, 2025(expired)· nominal 20-yr term from priority
Inventors:YANO YUJIISHIHARA SEIJI
H10W 90/754H10W 90/752H10W 90/734H10W 90/732H10W 90/724H10W 90/722H10W 90/291H10W 90/288H10W 90/271H10W 74/142H10W 74/117H10W 74/15H10W 74/00H10W 72/9415H10W 72/5445H10W 72/932H10W 72/923H10W 72/884H10W 72/877H10W 72/859H10W 72/90H10W 70/685H10W 70/682H10W 70/60H10W 90/701H10W 70/657H10W 70/614H10W 72/9445H10W 90/00
95
PatentIndex Score
76
Cited by
35
References
11
Claims

Abstract

A semiconductor device includes: a base substrate; a semiconductor chip formed on the base substrate in such a manner that an adhesive layer is interposed between the semiconductor chip and the base substrate; a resin layer covering at least a portion of the semiconductor chip; and an external connection terminal electrically connected to the base substrate via a wiring layer. The external connection terminal is in the same plane as the surface of the resin layer, and is exposed from the resin layer. With this configuration, it is possible to provide a semiconductor device of a lower stage, and a stacked semiconductor device, each of which is high in connection reliability in a case of stacking plural semiconductor devices, no matter if a connection terminal of a semiconductor device stacked on an upper stage is low.

Claims

exact text as granted — not AI-modified
1. A semiconductor device, comprising:
 a base substrate; 
 a semiconductor chip electrically coupled to the base substrate; 
 a supporting member attached to the semiconductor chip, wherein a wiring layer is formed on a surface of the supporting member opposite the semiconductor chip; 
 a resin layer covering at least portions of the semiconductor chip and the supporting member; and 
 a plurality of external connection terminals that are electrically coupled to the wiring layer, wherein surfaces of the external connection terminals are exposed from the resin layer, and wherein the exposed surfaces of the external connection terminals are substantially co-planer with an exterior surface of the resin layer. 
 
     
     
       2. The semiconductor device as set forth in  claim 1 , wherein bonding wires electrically couple the wiring layer to the base substrate. 
     
     
       3. The semiconductor device as set forth in  claim 1 , wherein:
 a first surface of the resin layer is depressed towards the base substrate so that the first surface is closer to the base substrate than a second surface of the resin layer is to the base substrate, 
 the first surface being a surface of the resin layer in a region where the external connection terminals are provided, and 
 the second surface being a surface of the resin layer other than the first surface. 
 
     
     
       4. The semiconductor device as set forth in  claim 1 , wherein said external connection terminals are made of a solder. 
     
     
       5. The semiconductor device as set forth in  claim 1 , wherein said external connection terminals are made of copper. 
     
     
       6. The semiconductor device as set forth in  claim 2 , wherein the bonding wires are encapsulated in the resin layer. 
     
     
       7. The semiconductor device as set forth in  claim 2 , wherein a plurality of solder bumps electrically couple the semiconductor chip to the base substrate. 
     
     
       8. The semiconductor device as set forth in  claim 2 , wherein bonding wires also electrically couple the semiconductor chip to the base substrate. 
     
     
       9. The semiconductor device as set forth in  claim 4 , wherein said solder has a melting point of 200° C. or higher. 
     
     
       10. The semiconductor device as set forth in  claim 8 , further comprising an adhesive layer that couples the supporting member to the semiconductor chip, wherein the bonding wires that electrically couple the semiconductor chip to the base substrate pass through the adhesive layer. 
     
     
       11. The semiconductor device as set forth in  claim 8 , further comprising a spacer position between the semiconductor chip and the supporting member, wherein the spacer provides sufficient space between the semiconductor chip and the supporting member to allow the bonding wires to pass, unobstructed, between the semiconductor chip and the base substrate.

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