System and method for controlling radio frequency transmissions from an electronic device

Abstract

The invention relates to a system and method for attenuating harmonics in output signals. In the system, an electronic circuit for reducing harmonics of an output signal from a power amplifier in a transmission circuit for a wireless communication device is provided. The circuit comprises: a printed circuit board (PCB); a power amplifier for generating an output signal; and a circuit implemented on the PCB connected to an output terminal of the power amplifier for the output signal. The circuit comprises a first filtering stage; a delay element; and a harmonic filter. The delay element is located between the harmonic filter and the output terminal and the delay element provides a timing delay in the output signal through at least one 0 ohm-rated component. Also, the harmonic filter is a low pass filter having a frequency cut-off point that attenuates first order harmonics of the output signal.

1. An electronic circuit for reducing harmonics of output signals from a power amplifier in a radio frequency transmission circuit for a wireless communication device, comprising:
 a printed circuit board (PCB); 
 a power amplifier for generating an output signal for said communication device through an output terminal; and 
 a circuit implemented on the PCB, said circuit connected to said output terminal and comprising:
 a filtering stage connected to said output terminal; 
 locations for components for a low pass filter, said low pass filter located after said filtering stage; 
 a harmonic filter located after said locations for said low pass filter and having a frequency cut-off point that attenuates first order harmonics of said output signal; and 
 a delay element populated in one location of said locations for components of said low pass filter, said one location providing a connection between said filtering stage and said harmonic filter, said delay element providing a timing delay for the output signal and comprising a 0 ohm rated component, 
 
 
       wherein components for said low pass filter are not populated in the remaining locations of said locations for components of said low pass filter. 
     
     
       2. The electronic circuit for reducing harmonics of an output signal from a power amplifier as claimed in  claim 1 , wherein said filtering stage comprises a notch filter to attenuate signals about the 5 GHz frequency band. 
     
     
       3. The electronic circuit for reducing harmonics of an output signal from a power amplifier as claimed in  claim 2 , wherein said filtering stage further comprises a second low pass filter to attenuate signals over the 5 GHz frequency band. 
     
     
       4. The electronic circuit for reducing harmonics of an output signal from a power amplifier as claimed in  claim 1 , wherein said delay element is an inductor. 
     
     
       5. The electronic circuit for reducing harmonics of an output signal from a power amplifier as claimed in  claim 1 , further comprising capacitors to reduce transmission of signals from said power amplifier in tracks in the PCB of a power connection circuit connecting the power amplifier to a battery for said amplifier. 
     
     
       6. The electronic circuit for reducing harmonics of an output signal from a power amplifier as claimed in  claim 5 , wherein a set of said capacitors are located in said power connection circuit between a high filter choke and said power amplifier. 
     
     
       7. The electronic circuit for reducing harmonics of an output signal from a power amplifier as claimed in  claim 6 , wherein said set of said capacitors provide a third low pass filter to attenuate signals over the 2 GHz frequency band. 
     
     
       8. The electronic circuit for reducing harmonics of an output signal from a power amplifier as claimed in  claim 6 , wherein a second set of said capacitors is located in said power connection circuit between said high filter choke and battery. 
     
     
       9. The electronic circuit for reducing harmonics of an output signal from a power amplifier as claimed in  claim 8 , wherein said second set of said capacitors provides a third low pass filter to attenuate signals over the 2 GHz frequency band. 
     
     
       10. The electronic circuit for reducing harmonics of an output signal from a power amplifier as claimed in  claim 5 , wherein an input point on said circuit is tuned to accommodate power and impedance characteristics of an output of said power amplifier. 
     
     
       11. A method of reducing harmonics of an output signal from a power amplifier in a radio frequency transmission circuit for a wireless communication device, comprising:
 providing a first filtering stage for said output signal; 
 providing locations for components for a low pass filter, said low pass filter located after said first filtering stage; 
 providing a harmonic filter after locations for components of said low pass filter to provide a second low pass filter having a frequency cut-off point that attenuates first order harmonics of said output signal; 
 providing an output stage for said output signal after said harmonic filter; and 
 providing a dedicated delay element in one location of said locations for components of said low pass filter, said one location providing a connection between said first filtering stage and said harmonic filter, said delay element providing a timing delay for the output signal and comprising a 0 ohm rated component, causing harmonics of the output signal to be reduced. 
 
     
     
       12. The method of reducing harmonics of an output signal from a power amplifier as claimed in  claim 11 , further comprising filtering transmission of signals from said power amplifier in a power connection circuit connecting the power amplifier to a battery for said amplifier. 
     
     
       13. The electronic circuit for reducing harmonics of an output signal from a power amplifier as claimed in  claim 1 , wherein said delay element is provided in a 0402 package. 
     
     
       14. An electronic circuit for reducing harmonics of an output signal from a power amplifier in a radio frequency transmission circuit for a wireless communication device, comprising:
 a printed circuit board (PCB); 
 a power amplifier for generating an output signal for said communication device; 
 a circuit implemented on the PCB, said circuit connected to an output terminal of said power amplifier for said output signal and comprising
 a filtering stage connected to said output terminal; 
 locations for components for a low pass filter, said low pass filter located after said filtering stage; 
 a harmonic filter located after said locations for said low pass filter and having a frequency cut-off point that attenuates first order harmonics of said output signal; and 
 a delay element populated in one location of said locations for components of said low pass filter, said one location providing a connection between said filtering stage and said harmonic filter, said delay element providing a timing delay for the output signal and comprising a 0 ohm rated component, and 
 
 capacitors to reduce transmission of signals from said power amplifer in tracks in the PCB of a power connection circuit connecting the power amplifier to a battery for said amplifier. 
 
     
     
       15. The electronic circuit for reducing harmonics of an output signal from a power amplifier as claimed in  claim 14 , wherein said filtering stage comprises a notch filter to attenuate signals about the 5 GHz frequency band. 
     
     
       16. The electronic circuit for reducing harmonics of an output signal from a power amplifier as claimed in  claim 14 , wherein said filtering stage further comprises a low pass filter to attenuate signals over the 5 GHz frequency band. 
     
     
       17. The electronic circuit for reducing harmonics of an output signal from a power amplifier as claimed in  claim 14 , wherein a set of said capacitors are located in said power connection circuit between a high filter choke and said power amplifier. 
     
     
       18. The electronic circuit for reducing harmonics of an output signal from a power amplifier as claimed in  claim 17 , wherein said set of said capacitors provide a low pass filter to attenuate signals over the 2 GHz frequency band.