Semiconductor memory device having split word line driver circuit with layout patterns that provide increased integration density

Abstract

Semiconductor memory devices having hierarchical word line structures are provided. A block of sub-word line driver circuits (SWDB) are disposed between a first block of memory and a second block of memory. A SWDB includes a plurality of sub-wordline driver (SWD) circuits arranged in a plurality of SWD columns each having four SWD circuits extending in a first direction between the first and second blocks of memory. Two adjacent SWD columns include a SWD group for driving a plurality of sub-word lines extending from the SWD group along the first direction into the first and second blocks of memory.

1. A semiconductor memory device, comprising:
 a block of sub-word line driver circuits (SWDB) disposed between a first block of memory and a second block of memory, 
 wherein the SWDB comprises a plurality of sub-wordline driver (SWD) circuits arranged in a plurality of SWD columns each comprising four SWD circuits extending in a first direction between the first and second blocks of memory, 
 wherein two adjacent SWD columns comprises a SWD group for driving sub-word lines extending from the SWD group along the first direction into the first block of memory and for driving sub-word lines extending from the SWD group along the first direction into the second block of memory, 
 wherein each of a first pair of SWD circuits in a first SWD column of the two adjacent columns and each of a first pair of SWD circuits in a second SWD column of the two adjacent columns share first common word line activation control signals, and 
 wherein each of a second pair of SWD circuits in the first SWD column of the two adjacent columns and each of a second pair of SWD circuits in the second column of the two adjacent columns share second common word line activation signals. 
 
   
   
     2. The semiconductor memory device of  claim 1 , wherein each SWD group drives even sub-wordlines extending into the first and second blocks of memory. 
   
   
     3. The semiconductor memory device of  claim 1 , wherein each SWD group drives odd sub-wordlines extending into the first and second blocks of memory. 
   
   
     4. The semiconductor memory device of  claim 1 , wherein each SWD circuit comprises a first transistor, a second transistor, a third transistor and a fourth transistor, wherein the first transistor of at least four SWD circuits of a given SWD group are arranged adjacent to each other and share an active region. 
   
   
     5. The semiconductor memory device of  claim 4 , wherein the first transistors have control gate electrodes that are substantially L-shaped. 
   
   
     6. The semiconductor device of  claim 4 , wherein the second transistor of at least four SWD circuits of a given SWD group are arranged adjacent to each other and share and a ground node. 
   
   
     7. The semiconductor device of  claim 6 , wherein the second transistors are arranged in a central region of the SWDB between the first and second memory blocks. 
   
   
     8. The semiconductor device of  claim 1 , wherein four sub wordlines and two normal word lines are formed on upper layers over each SWD column extending in a direction of the SWD column. 
   
   
     9. The semiconductor device of  claim 1 , wherein the semiconductor device is a DRAM. 
   
   
     10. A semiconductor DRAM (dynamic random access memory) device, comprising:
 a plurality of separately controlled memory banks, wherein each memory bank comprises: 
 a matrix of separate memory blocks extending in column and row directions over the memory bank; 
 a block of row decoder circuits disposed along one side of the memory bank, 
 a set of n normal wordlines extending from each block of row decoder circuits along each row of memory blocks of the memory bank; 
 a block of sub-word line driver circuits (SWDB) disposed between each memory block in row direction of the memory bank and connected to each set of n normal wordlines extending along the given row of memory blocks, 
 wherein each SWDB comprises a plurality of sub-wordline driver (SWD) circuits arranged in a plurality of SWD columns each comprising four SWD circuits extending in a first direction between the first and second blocks of memory, 
 wherein two adjacent SWD columns comprises a SWD group for driving sub-word lines extending from the SWD group along the first direction into the first block of memory and for driving sub-word lines extending from the SWD group along the first direction into the second block of memory, 
 wherein each of a first pair of SWD circuits in a first SWD column of the two adjacent columns and each of a first pair of SWD circuits in a second SWD column of the two adjacent columns share first common word line activation control signals, and 
 wherein each of a second pair of SWD circuits in the first SWD column of the two adjacent columns and each of a second pair of SWD circuits in the second column of the two adjacent columns share second common word line activation signals. 
 
   
   
     11. The semiconductor memory device of  claim 10 , wherein each SWD group drives even sub-wordlines extending into first and second memory blocks on each side of the SWD group in the row direction. 
   
   
     12. The semiconductor memory device of  claim 10 , wherein each SWD group drives odd sub-wordlines extending into first and second memory blocks on each side of the SWD group in the row direction. 
   
   
     13. The semiconductor memory device of  claim 10 , wherein each SWD circuit comprises a first transistor, a second transistor, a third transistor and a fourth transistor, wherein the first transistor of at least four SWD circuits of a given SWD group are arranged adjacent to each other and share an active region. 
   
   
     14. The semiconductor memory device of  claim 13 , wherein the first transistors have control gate electrodes that are substantially L-shaped. 
   
   
     15. The semiconductor device of  claim 13 , wherein the second transistor of at least four SWD circuits of a given SWD group are arranged adjacent to each other and share and a ground node. 
   
   
     16. The semiconductor device of  claim 15 , wherein the second transistors are arranged in a central region of the SWDB between the first and second memory blocks. 
   
   
     17. The semiconductor device of  claim 10 , wherein four sub wordlines and two normal word lines are formed on upper layers over each SWD column extending in a direction of the SWD column.