High speed level shifter

Abstract

The invention relates to a level shifter comprising an input stage having a parasitic capacitance and a first input terminal for applying an input signal, a limiter stage having a second input terminal for applying a switching signal, wherein said input stage is coupled between a first supply terminal and said limiter stage, an output stage being coupled between a second supply terminal and said limiter stage and providing an output signal which is a level shifted version of said input signal, and a current source being adapted for injecting a current pulse into said parasitic capacitance dependent on variations of said switching signal over time.

1. A level shifter comprising:
 an input stage having a parasitic capacitance and a first input terminal for receiving an input signal; 
 a limiter stage having a second input terminal for receiving a switching signal, wherein said input stage is coupled between a first supply terminal and said limiter stage; 
 an output stage being coupled between a second supply terminal and said limiter stage, the output stage providing an output signal that is a level shifted version of said input signal; and 
 a current source adapted to inject a current pulse into said parasitic capacitance dependent on variations of said switching signal over time. 
 
   
   
     2. The level shifter of  claim 1 , wherein said input stage comprises a first transistor and a second transistor each having a control terminal, a first load terminal and a second load terminal, wherein said second load terminals of said first and said second transistors are both coupled to said first supply terminal for receiving a first supply potential, and wherein said first load terminals of said first and said second transistors are coupled to a first and a second node, respectively. 
   
   
     3. The level shifter of  claim 2 , wherein said limiter stage comprises a third transistor and a fourth transistor each having a control terminal and a load path, wherein said load paths of said third and said fourth transistor are coupled to said first and said second nodes, respectively, and wherein said control terminals of said third and said fourth transistor are coupled to said second input terminal. 
   
   
     4. The level shifter of  claim 3 , wherein said output stage comprises a fifth transistor and a sixth transistor each having a control terminal and a load path, wherein said load paths of said fifth and sixth transistors are coupled in series with said load paths of said third and fourth transistors, respectively, and wherein said control terminal of said fifth transistor is coupled to a load terminal of said sixth transistor and vice versa. 
   
   
     5. The level shifter of  claim 4 , wherein first load terminals of said fifth and said sixth transistors are coupled to said second supply terminal, and said output signal is provided by a second load terminal of said fifth transistor. 
   
   
     6. The level shifter of  claim 1 , wherein said current source is adapted to detect an edge of said switching signal and to inject a current pulse into said parasitic capacitance when the edge is detected. 
   
   
     7. The level shifter of  claim 1 , wherein said current source comprises a current mirror having a first branch and a second branch, said first branch being electrically coupled to said first supply potential via a capacitor and said second branch being coupled to said parasitic capacitance. 
   
   
     8. The level shifter of  claim 7 , wherein said current mirror comprises a seventh transistor and an eighth transistor, said seventh transistor being coupled to said capacitor and said eighth transistor being coupled to said parasitic capacitance. 
   
   
     9. The level shifter of  claim 7 , wherein said capacitor has a capacitance value that is chosen such that in case of a rising edge in said switching signal, said current pulse is delivered to said parasitic capacitance, the total charge of said current pulse sufficing to charge said parasitic capacitance substantially up to its steady state voltage level. 
   
   
     10. A power converter comprising:
 the level shifter of  claim 1 ; 
 a floating driver circuit coupled to the output signal of the level shifter; 
 a semiconductor switch comprising
 a control node coupled to an output of the floating circuit driver, 
 a second node coupled to a supply potential, and 
 a third node coupled to a power supply output; and 
 
 a regulator coupled between the power supply output and the level shifter, the regulator producing a pulse-width modulated signal. 
 
   
   
     11. A semiconductor arrangement comprising
 a semiconductor switch; 
 a floating driver circuit coupled to a control terminal of said semiconductor switch for controlling a potential of said control terminal; and 
 a level shifter coupled between a first input terminal for applying an input signal and said floating driver circuit, the level shifter comprising:
 an input stage having a parasitic capacitance and a first input terminal for receiving an input signal; 
 a limiter stage having a second input terminal for receiving a switching signal, wherein said input stage is coupled between a first supply terminal and said limiter stage; 
 an output stage being coupled between a second supply terminal and said limiter stage, the output stage providing an output signal that is a level shifted version of said input signal, the output signal being coupled to an input of the floating driver circuit; and 
 a current source adapted to inject a current pulse into said parasitic capacitance dependent on variations of said switching signal over time. 
 
 
   
   
     12. The semiconductor arrangement of  claim 11 , further comprising a bootstrap supply circuit coupled to a third supply terminal for applying a third supply potential and being adapted to provide a second supply potential at said second supply terminal. 
   
   
     13. The semiconductor arrangement of  claim 11 , wherein said input stage comprises a first transistor and a second transistor each having a control terminal, a first load terminal and a second load terminal, wherein said second load terminals of said first and said second transistors are both coupled to said first supply terminal for receiving a first supply potential, and wherein said first load terminals of said first and said second transistors are coupled to a first and a second node respectively. 
   
   
     14. The semiconductor arrangement of  claim 13 , wherein said limiter stage comprises a third transistor and a fourth transistor, each having a control terminal and a load path, wherein said load paths of said third and said fourth transistor are coupled to said first and said second nodes, respectively, and wherein said control terminals of said third and said fourth transistor are coupled to said second input terminal. 
   
   
     15. The semiconductor arrangement of  claim 14 , wherein said output stage comprises a fifth transistor and a sixth transistor, each having a control terminal and a load path, wherein said load paths of said fifth and sixth transistors are coupled in series with said load paths of said third and fourth transistors respectively, and wherein said control terminal of said fifth transistor is coupled to a load terminal of said sixth transistor and vice versa. 
   
   
     16. The semiconductor arrangement of  claim 15 , wherein first load terminals of said fifth and said sixth transistors are coupled to said second supply terminal, and said output signal is provided by a second load terminal of said fifth transistor. 
   
   
     17. The semiconductor arrangement of  claim 11 , wherein said current source is adapted to detect an edge of said switching signal and to inject a current pulse into said parasitic capacitance when the edge is detected. 
   
   
     18. The semiconductor arrangement of  claim 11 , wherein said current source comprises a current mirror having a first branch and a second branch, said first branch being electrically coupled to said first supply potential via a capacitor and said second branch being coupled to said parasitic capacitance. 
   
   
     19. The semiconductor arrangement of  claim 18 , wherein said current mirror comprises a seventh transistor and an eighth transistor, said seventh transistor being coupled to said capacitor and said eighth transistor being coupled to said parasitic capacitance. 
   
   
     20. The semiconductor arrangement of  claim 18 , wherein said capacitor has a capacitance value that is chosen such that in case of a rising edge in said switching signal, said current pulse is delivered to said parasitic capacitance, the total charge of said current pulse sufficing to charge said parasitic capacitance substantially up to its steady state voltage level. 
   
   
     21. A circuit comprising:
 a first transistor with a control terminal coupled to an input node, the first transistor having a current path between a first supply terminal and a first circuit node; 
 a second transistor with a control terminal coupled to an inverted input node, the second transistor having a current path between the first supply terminal and a second circuit node; 
 a third transistor with a control terminal coupled to a switching signal node, the third transistor having a current path between the first circuit node and a third circuit node; 
 a fourth transistor with a control terminal coupled to the control terminal of the third transistor, the fourth transistor having a current path between the second circuit node and a fourth circuit node; 
 a fifth transistor with a control terminal coupled to the fourth circuit node, the fifth transistor having a current path between the third circuit node and a bootstrap supply potential node; 
 a sixth transistor with a control terminal coupled to the third circuit node, the sixth transistor having a current path between the fourth circuit node and the bootstrap supply potential node; and 
 a current source coupled between the second circuit node and the bootstrap supply potential node to inject a current into a parasitic capacitance coupled to the second circuit node, the current being dependent on variations of a signal coupled to the signal switching node.