Semiconductor memory device with internal voltage generating circuit and method for operating the same

Abstract

Semiconductor memory device with internal voltage generating circuit and method for operating the same includes a high voltage detecting circuit configured to detect a voltage level of a high voltage and activate a pumping determining signal when the voltage level of the high voltage is below a predetermined level; a pumping circuit configured to perform a pumping operation in response to the pumping determining signal and an active signal; and an auxiliary pumping circuit configured to perform the pumping operation in response to the pumping determining signal and a bank active pulse signal.

1. A semiconductor memory device, comprising:
 a high voltage detecting circuit configured to detect a voltage level of a high voltage and activate a pumping determining signal when the voltage level of the high voltage is below a predetermined level; 
 a pumping circuit configured to perform a pumping operation in response to the pumping determining signal and an active signal; and 
 an auxiliary pumping circuit configured to perform the pumping operation in response to the pumping determining signal and a bank active pulse signal. 
 
   
   
     2. The semiconductor memory device as recited in  claim 1 , wherein the active signal is activated during an activation duration of the active signal, and the bank active pulse signal is a reference pulse signal when activating the active signal. 
   
   
     3. The semiconductor memory device as recited in  claim 1 , wherein the pumping circuit comprises:
 an active pumping unit configured to perform the pumping operation in response to the pumping determining signal and the active signal; and 
 a standby pumping unit configured to perform the pumping operation in response to the pumping determining signal. 
 
   
   
     4. The semiconductor memory device as recited in  claim 1 , wherein the auxiliary pumping circuit comprises:
 an auxiliary pumping control unit configured to output an auxiliary pumping enable signal having a predetermined activation duration according to the activation of the pumping determining signal when the bank active pulse signal is received; and 
 an auxiliary pumping unit configured to perform the pumping operation in response to the auxiliary pumping enable signal. 
 
   
   
     5. The semiconductor memory device as recited in  claim 4 , wherein the auxiliary pumping control unit comprises:
 an edge trigger configured to transfer the pumping determining signal in response to the bank active pulse signal; 
 a state latch configured to latch an output signal of the edge trigger when the auxiliary pumping enable signal is deactivated after application of a power supply voltage; and 
 a pulse generator configured to receive an output signal of the state latch to generate the auxiliary pumping enable signal having the predetermined activation duration. 
 
   
   
     6. The semiconductor memory device as recited in  claim 5 , wherein the edge trigger comprises:
 a cross-coupled latch configured to receive the pumping determining signal and an inverted pumping determining signal; and 
 a biasing unit configured to enable the cross-coupled latch in response to the bank active pulse signal. 
 
   
   
     7. The semiconductor memory device as recited in  claim 5 , wherein the state latch comprises:
 a power supply driver configured to transfer a power supply voltage in response to a power-up signal indicating the application of the power supply voltage; 
 an inverter configured to invert the output signal of the edge trigger in response to an output signal of the pulse generator; and 
 a latch configured to latch an output signal of the inverter and an output signal of the power supply driver. 
 
   
   
     8. The semiconductor memory device as recited in  claim 5 , wherein the pulse generator comprises:
 a delay configured to delay the output signal of the state latch during a predetermined time corresponding to the activation duration of the auxiliary pumping enable signal; and 
 a logic gate configured to perform a logic operation on the output signal of the state latch and an output signal of the delay to generate a pulse. 
 
   
   
     9. The semiconductor memory device as recited in  claim 8 , wherein the delay comprises an even number of inverters connected in series. 
   
   
     10. The semiconductor memory device as recited in  claim 8 , wherein the delay comprises:
 an even number of inverters connected in series; 
 a NAND gate configured to perform a NAND operation on an input signal and an output signal of the inverters; and 
 an inverter configured to invert an output signal of the NAND gate. 
 
   
   
     11. The semiconductor memory device as recited in  claim 4 , wherein the auxiliary pumping control unit comprises:
 a pulse adjusting unit configured to adjust an activation duration of the bank active pulse signal 
 an edge trigger configured to transfer the activated pumping determining signal in response to an output signal of the pulse adjusting unit; 
 a state latch configured to latch an output signal of the edge trigger when the auxiliary pumping enable signal is deactivated after application of a power supply voltage; and 
 a pulse generator configured to receive an output signal of the state latch to generate the auxiliary pumping enable signal having the predetermined activation duration. 
 
   
   
     12. The semiconductor memory device as recited in  claim 11 , wherein the pulse adjusting unit comprises:
 an inverter configured to invert the bank active pulse signal; 
 a plurality of inverters configured to delay an output signal of the inverter; and 
 a NAND gate configured to perform a NAND operation on the output signal of the inverter and an output signal of the plurality of inverters. 
 
   
   
     13. The semiconductor memory device as recited in  claim 4 , wherein the predetermined time is longer than a period of the bank active pulse signal. 
   
   
     14. A semiconductor memory device, comprising:
 a plurality of banks using a high voltage; 
 a high voltage detecting unit configured to detect a voltage level of the high voltage and activate a pumping determining signal when the voltage level of the high voltage is below a predetermined level; and 
 a pumping circuit configured to perform a pumping operation in response to the pumping determining signal and a bank active pulse signal indicating a timing point when the banks are enabled for performing a read/write operation. 
 
   
   
     15. The semiconductor memory device as recited in  claim 14 , further comprising:
 a standby pumping unit configured to perform the pumping operation in response to the pumping determining signal; and 
 an active pumping unit configured to perform the pumping operation in response to the pumping determining signal and an active signal. 
 
   
   
     16. The semiconductor memory device as recited in  claim 14 , wherein the pumping circuit comprises:
 an auxiliary pumping control unit configured to output an auxiliary pumping enable signal having a predetermined activation duration according to the activation of the pumping determining signal when the bank active pulse signal is received; and 
 an auxiliary pumping unit configured to perform the pumping operation in response to the auxiliary pumping enable signal. 
 
   
   
     17. The semiconductor memory device as recited in  claim 16 , wherein the auxiliary pumping control unit comprises:
 an edge trigger configured to transfer the pumping determining signal in response to the bank active pulse signal; 
 a state latch configured to latch an output signal of the edge trigger when the auxiliary pumping enable signal is deactivated after application of a power supply voltage; and 
 a pulse generator configured to receive an output signal of the state latch to generate the auxiliary pumping enable signal having the predetermined activation duration. 
 
   
   
     18. A method for operating a semiconductor memory device, the method comprising:
 detecting a voltage level of a high voltage and activating a pumping determining signal when the detected voltage level of the high voltage is below a predetermined level; 
 performing a pumping operation in response to the pumping determining signal and a bank active pulse signal indicating a timing point when the banks are enabled for performing a read/write operation; and 
 performing a read operation and a write operation by using the high voltage. 
 
   
   
     19. The method as recited in  claim 18 , further comprising:
 performing the pumping operation in response to the pumping determining signal and an active signal. 
 
   
   
     20. The method as recited in  claim 18 , wherein the performing of the pumping operation comprises:
 outputting an auxiliary pumping enable signal having a predetermined activation duration according to activation of the pumping determining signal when a bank active pulse signal is received; and 
 performing the pumping operation in response to the auxiliary pumping enable signal.