Flash memory with multi-bit read

Abstract

A memory device is described that uses extra data bits stored in a multi-level cell (MLC) to provide error information. An example embodiment provides a memory cell that uses more than 2 X logic levels to store X data bits and an error bit. At least one extra bit provided during a read operation is used to provide error information or a confidence factor of the X data bits originally stored in the cell.

1. A memory device comprising:
 a multilevel memory cell configured to store more than 2 X  data levels representing X units of information, wherein at least one unit of the X units represents an error unit; and 
 a decoder configured to decode the 2 X  data levels and determine a confidence factor for the X units based upon the error unit. 
 
   
   
     2. The memory device of  claim 1 , wherein the more than 2 X  data levels include at least a first data level and a second data level decodable as data units with a high confidence factor, while at least a portion of the remaining data levels are decodable as data units with a low confidence factor. 
   
   
     3. The memory device of  claim 2 , wherein at least the first data level and the second data level represent strong states, and at least a portion of the remaining data levels represent weak states. 
   
   
     4. The memory device of  claim 1 , wherein the decoder includes an error correction circuit to correct data errors identified by the confidence factor. 
   
   
     5. The memory device of  claim 1 , wherein the multilevel memory cell is a NAND memory cell. 
   
   
     6. A device, comprising:
 a memory cell programmable to one of more than 2 X  logic states; and 
 a decoder configured to decode an output from the memory cell, wherein the decoder decodes one of the more than 2 X  logic states into X data units and determines a confidence factor for the X data units based upon a selected data unit decoded from the one of the more than 2 X  logic states. 
 
   
   
     7. The system of  claim 6 , wherein the confidence factor is based upon a most significant bit (MSB) decoded from the X data units. 
   
   
     8. The memory device of  claim 6 , wherein the decoder includes an error correction circuit to correct data errors identified by the confidence factor. 
   
   
     9. The memory device of  claim 6 , wherein the multilevel memory cell is a NAND memory cell. 
   
   
     10. A memory device, comprising:
 a multilevel memory cell configured to store data levels corresponding to distinct logic states; 
 a control circuit configured to program the multilevel memory cell to the distinct logic states, wherein the logic states include a least significant bit (LSB) and a most significant bit (MSB); and 
 a decoder circuit configured to decode the memory cell, wherein the decoder reads the data without error when the LSB of the data and the MSB of the data are equal, and detects an error when the LSB and the MSB are not equal. 
 
   
   
     11. The memory device of  claim 10 , wherein the LSB is an information unit of the data, and the MSB is an information unit corresponding to an error unit. 
   
   
     12. The memory device of  claim 10 , comprising an error correction circuit configured to correct an error identified by the decoder. 
   
   
     13. The memory device of  claim 10 , wherein the multilevel memory cell comprises a non-volatile memory cell. 
   
   
     14. A system comprising:
 a memory comprising multilevel memory cells programmable to one of more than 2 X  states; and 
 a decoder configured to decode one of the more than 2 X  states into X data units and determines a confidence factor for the X data units based upon a selected data unit decoded from the one of the more than 2 X  states. 
 
   
   
     15. The system of  claim 14 , wherein the confidence factor is based upon a most significant bit (MSB) decoded from the X data units. 
   
   
     16. The system of  claim 14 , wherein the confidence factor is based upon a comparison between the most significant bit (MSB) and a least significant bit (LSB) decoded from the X data units. 
   
   
     17. The system of  claim 14 , wherein the confidence factor includes a high value and a low value, further comprising an error correction circuit configured to correct the X data units when the confidence factor has a low value. 
   
   
     18. The system of  claim 14 , wherein the confidence factor includes a high value and a low value, and the X data units are decoded as free from errors when the confidence factor has a high value. 
   
   
     19. The memory device of  claim 14 , wherein the multilevel memory cell is a NAND memory cell. 
   
   
     20. A method of storing data comprising:
 storing X units of data as one of more than 2 X  logic states in a memory device; 
 reading one of the more than 2 X  logic states from the memory device; and 
 decoding the one of the more than 2 X  data states to provide the X units of data that include at least one unit determining a confidence factor for the X bits. 
 
   
   
     21. The method of  claim 20 , wherein decoding the one of the more than 2 X  data states comprises determining a high value and a low value for the confidence factor, wherein the high value indicates the X units of data are substantially error free, and a low value indicates the X units of data include an error. 
   
   
     22. The method of  claim 20 , wherein determining a high value and a low value for the confidence factor comprises comparing a least significant bit (LSB) and a most significant bit (MSB) for the X units of data, further wherein the LSB and the MSB are equal when the data are substantially error free. 
   
   
     23. The method of  claim 20 , wherein determining a high value and a low value for the confidence factor comprises determining a value for the MSB to determine if an error is present in the X units of data. 
   
   
     24. A method of operating a memory device comprising:
 storing data in a multi-level cell (MLC) memory device, wherein each memory cell has discrete state levels defining at least a first and a second information unit; and 
 decoding data read from the memory device, wherein the second information bit indicates a confidence factor for the read data. 
 
   
   
     25. The method of  claim 24 , wherein decoding data read from the memory device comprises determining a high value and a low value for the confidence factor, wherein the high value indicates the data is substantially error free, and a low value indicates the data includes an error.