P
US7747400B2ActiveUtilityPatentIndex 91

VA metering in polyphase systems

Assignee: LANDIS & GYR INCPriority: Oct 6, 2006Filed: Oct 9, 2007Granted: Jun 29, 2010
Est. expiryOct 6, 2026(~0.3 yrs left)· nominal 20-yr term from priority
Inventors:VOISINE JOHN
G01R 21/1331
91
PatentIndex Score
27
Cited by
13
References
12
Claims

Abstract

An arrangement includes an A/D converter and a processing circuit. The A/D converter is configured to generate digital samples of voltage and current waveforms in a polyphase electrical system. The processing circuit is operably coupled to receive the digital samples from the A/D converter. The processing circuit is further configured to combine a value substantially equal to two times the magnitude of the phase A current sample with the phase C current sample to generate a first value, and generate a VA calculation using the first value and at least one other value. The processing circuit is further configured to provide information representative of the VA calculation to one of a group consisting of a display, a communication circuit, and a billing calculation unit.

Claims

exact text as granted — not AI-modified
1. An arrangement, comprising:
 a) an A/D converter configured to generate digital samples of voltage and current waveforms in a polyphase electrical system; 
 b) a processing circuit operably coupled to receive the digital samples from the A/D converter, the processing circuit configured to:
 i) generate a VA calculation using the following relationship 
 
 
     
       
         
           
             
               VA 
               Source 
             
             = 
             
               
                 1 
                 3 
               
               ⁡ 
               
                 [ 
                 
                   
                     
                        
                       
                         
                           
                             I 
                             → 
                           
                           A 
                         
                         + 
                         
                           2 
                           ⁢ 
                           
                             
                               I 
                               → 
                             
                             C 
                           
                         
                       
                        
                     
                     · 
                     
                        
                       
                         
                           V 
                           → 
                         
                         CB 
                       
                        
                     
                   
                   + 
                   
                     
                        
                       
                         
                           2 
                           ⁢ 
                           
                             
                               I 
                               → 
                             
                             A 
                           
                         
                         + 
                         
                           
                             I 
                             → 
                           
                           C 
                         
                       
                        
                     
                     · 
                     
                        
                       
                         
                           V 
                           → 
                         
                         AB 
                       
                        
                     
                   
                   + 
                   
                     
                        
                       
                         
                           
                             I 
                             → 
                           
                           A 
                         
                         - 
                         
                           
                             I 
                             → 
                           
                           C 
                         
                       
                        
                     
                     · 
                     
                        
                       
                         
                           
                             V 
                             → 
                           
                           AB 
                         
                         - 
                         
                           
                             V 
                             → 
                           
                           CB 
                         
                       
                        
                     
                   
                 
                 ] 
               
             
           
         
       
     
     where {right arrow over (I)} A  is the current vector on phase A, {right arrow over (I)} C  is the current vector on phase C, {right arrow over (V)} CB  is the voltage vector across phase C and phase B, and {right arrow over (V)} AB  is the voltage vector across phase A and phase B;
 ii) provide information representative of the VA calculation to one of a group consisting of a display, a communication circuit, and a billing calculation unit. 
 
   
   
     2. The arrangement of  claim 1 , wherein the processing circuit is further configured to generate a first value representative of {right arrow over (I)} A +2{right arrow over (I)} C  at least in part by combining a value substantially equal to two times the magnitude of a phase C current sample with a phase A current sample. 
   
   
     3. The arrangement of  claim 2 , wherein the processing circuit is further configured to generate a second value representative of {right arrow over (V)} CB  based at least in part on phase C voltage samples. 
   
   
     4. The arrangement of  claim 3 , wherein the processing circuit is further configured to generate a value representative of a product of the first value and the second value. 
   
   
     5. The arrangement of  claim 1 , wherein the processing circuit is further configured to generate a first value representative of 2{right arrow over (I)} A +{right arrow over (I)} C  by combining two phase A current samples with a phase C current sample. 
   
   
     6. The arrangement of  claim 1 , further comprising the display, and wherein the display is configured to display the information representative of the VA calculation. 
   
   
     7. An arrangement, comprising:
 a) an A/D converter configured to generate digital samples of voltage and current waveforms in a polyphase electrical system; 
 b) a processing circuit operably coupled to receive the digital samples from the A/D converter, the processing circuit configured to:
 i) generate a first value at least in part by combining a value substantially equal to two times the magnitude of a phase C current sample with a phase A current sample; 
 ii) generate a VA calculation using the first value and at least one other value; 
 iii) provide information representative of the VA calculation to one of a group consisting of a display, a communication circuit, and a billing calculation unit. 
 
 
   
   
     8. The arrangement of  claim 7 , wherein the processing circuit is further configured to combine two phase A current samples with the phase C current sample to generate one of the at least one other values. 
   
   
     9. The arrangement of  claim 7 , wherein the processing circuit is further configured to generate a second value representative of a voltage difference between phase C and phase B based at least in part on phase C voltage samples. 
   
   
     10. The arrangement of  claim 9 , wherein the processing circuit is further configured to generate a value representative of a product of the first value and the second value. 
   
   
     11. The arrangement of  claim 7 , further comprising the display, and wherein the display is configured to display the information representative of the VA calculation. 
   
   
     12. The arrangement of  claim 7 , further comprising the communication circuit.

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