Clock selection circuit and synthesizer

Abstract

A clock selection circuit and synthesizer that is capable of selecting an optimum clock signal from among a plurality of clock signals in a short time. A reference-clock counter counts clock pulses in an inputted reference clock signal (REF). A clock counter counts clock pulses in one of the plurality of clock signals which is selected by a selection unit and frequency-divided by a frequency divider. An instruction-signal output unit outputs a plurality of comparison-instruction signals during an interval in which a difference occurs between the counts of two of the plurality of clock signals having the closest frequencies. A comparison unit compares the count of the reference-clock counter and the count of the clock counter. The selection unit selects a clock signal by a binary search according to the result of the comparison.

1. A clock selection circuit for selecting a clock signal from among a plurality of clock signals having different frequencies, comprising:
 a reference-clock counter which counts clock pulses in a reference clock signal and obtains a first count; 
 a clock counter which counts clock pulses in a frequency-divided clock signal which is produced by selecting and frequency-dividing one of said plurality of clock signals and obtains a second count; 
 a comparison unit which makes a first comparison of said first count and said second count to detect a difference therebetween, each time a comparison instruction signal is received; 
 a selection unit which makes a selection of said clock signal as a source of the frequency-divided clock signal, by a binary search according to a result of said first comparison; and 
 an instruction-signal output unit which repetitively outputs the comparison-instruction signal to the comparison unit until the difference between said first and second counts reaches a predetermined value, in each phase of the binary search during which the selection unit maintains the selection that has been made. 
 
   
   
     2. The clock selection circuit according to  claim 1 , wherein said selection unit selects said clock signal by said binary search when said first count and said second count are different. 
   
   
     3. The clock selection circuit according to  claim 1 , wherein said selection unit terminates said selection when said first count and said second count are identical. 
   
   
     4. The clock selection circuit according to  claim 1 , further comprising:
 a clock-information storing unit which stores a first time which elapses until the difference between said first count and said second count reaches the predetermined value in a phase preceding to a current phase of said binary search; and 
 a clock-information comparison unit which makes a second comparison of said first time and a second time which elapses until a difference between said first count and said second count reaches said predetermined value in the current phase after completion of said binary search, 
 wherein said selection unit selects, as a source of said frequency-divided clock signal, one of clock signals selected in the current phase and the phase preceding to the current phase based on a result of said second comparison. 
 
   
   
     5. The clock selection circuit according to  claim 4 , wherein said selection unit selects said one of said clock signals selected in the current phase and the phase preceding to the current phase, corresponding to a longer one of said first time and said second time. 
   
   
     6. The clock selection circuit according to  claim 4 , wherein the current phase coincides with a final phase of said binary search. 
   
   
     7. The clock selection circuit according to  claim 6 , wherein the phase is immediately preceding to the current phase. 
   
   
     8. The clock selection circuit according to  claim 1 , wherein said instruction-signal output unit outputs said plurality of comparison-instruction signals at timings which are determined so that said comparison unit can correctly make said first comparison even when asynchronism between said plurality of clock signals and said reference clock signal causes an error in said first count or said second count. 
   
   
     9. The clock selection circuit according to  claim 1 , wherein said comparison unit determines that said first count and said second count are identical when a difference between the first count and the second count is within a predetermined range. 
   
   
     10. The clock selection circuit according to  claim 1 , wherein said frequency-divided clock signal is produced at a frequency-division ratio which can be changed in accordance with an external instruction. 
   
   
     11. A clock selection circuit for selecting a clock signal from among a plurality of clock signals having different frequencies, comprising:
 a reference-clock counter which counts clock pulses in a frequency-divided reference clock signal and obtains a first count; 
 a clock counter which counts clock pulses in a selected one of said plurality of clock signals and obtains a second count; 
 a comparison unit which makes a comparison of said first count and said second count to detect a difference therebetween, each time a comparison instruction signal is received; 
 a selection unit which makes a selection of said clock signal for the clock counter by a binary search according to a result of said comparison; and 
 an instruction-signal output unit which repetitively outputs the comparison-instruction signal to the comparison unit until the difference between said first and second counts reaches a predetermined value, in each phase of the binary search during which the selection unit maintains the selection that has been made. 
 
   
   
     12. A synthesizer for selecting a clock signal from among a plurality of clock signals outputted from a plurality of voltage controlled oscillators, the synthesizer comprising:
 a reference-clock counter which counts clock pulses in a reference clock signal and obtains a first count; 
 a clock counter which counts clock pulses in a frequency-divided clock signal which is produced by selecting and frequency-dividing a first one of said plurality of clock signals and obtains a second count; 
 a comparison unit which makes a comparison of said first count and said second count to detect a difference therebetween, each time a comparison instruction signal is received; 
 a selection unit which makes a selection of said clock signal as a source of the frequency-divided clock signal, by a binary search according to a result of said comparison; 
 an instruction-signal output unit which repetitively outputs the comparison-instruction signal to the comparison unit until the difference between said first and second counts reaches a predetermined value, in each phase of the binary search during which the selection unit maintains the selection that has been made; and 
 a voltage control unit which controls a voltage controlling one of said plurality of voltage controlled oscillators which outputs said clock signal, according to a phase difference between said frequency-divided clock signal and said reference clock signal.