Time delay circuit for use in a reset circuit

Abstract

A time delay circuit for providing a time delay to a reset circuit includes a first circuit, a second circuit, an AND gate and a control signal input. The first circuit includes a first resistor and a first capacitor. The second circuit includes a second resistor and a second capacitor. The AND gate includes a first input, a second input and an output. The first capacitor includes an input coupled to a power source via the first resistor, and an output grounded. The second capacitor includes an input coupled to the control signal input and an output grounded. The first input of the AND gate is coupled to the input of the first capacitor, the second input coupled to the input of the second capacitor, and the output configured for coupling to a integrated circuit to reset.

1. A time delay circuit for providing a time delay to a reset circuit, the time delay circuit comprising:
 a control signal input; 
 a first circuit comprising:
 a first resistor comprising an output and an input coupled to a power source; and 
 a first capacitor comprising an input coupled the output of the first resistor and an output coupled to ground; 
 
 a second circuit comprising:
 a second resistor comprising an input coupled to the power source and an output coupled to the control signal input, and 
 a second capacitor comprising an input coupled to the control signal input and an output coupled to ground; and 
 
 an AND gate comprising a first input coupled to the input of the first capacitor, a second input coupled to the input of the second capacitor, and an output configured for coupling to an integrated circuit to control the integrated circuit to reset. 
 
     
     
       2. The time delay circuit as claimed in  claim 1 , wherein charging times of the first capacitor and the second capacitor are greater than a rest time of the integrated circuit. 
     
     
       3. The time delay circuit as claimed in  claim 1 , wherein the control signal input is configured for coupling to a watchdog chip, the watchdog chip configured for detecting running errors of the integrated circuit, and sending a reset signal to the control signal input so as to provide a low level signal to the second input of the AND gate, such that the AND gate outputs a low level signal to reset the integrated circuit. 
     
     
       4. The time delay circuit as claimed in  claim 3 , wherein the reset signal is a low signal input. 
     
     
       5. The time delay circuit as claim in  claim 3 , wherein the signal input and the low level signal are about 0 volts. 
     
     
       6. A time delay circuit for providing a time delay to a reset circuit, the time delay circuit comprising:
 a control signal input; 
 a first circuit comprising:
 a first resistor comprising an output and an input coupled to a power source; and 
 a first capacitor comprising an input coupled the output of the first resistor and an output coupled to ground; 
 
 a second circuit comprising:
 a second resistor comprising an input coupled to the power source and an output coupled to the control signal input, and 
 a second capacitor comprising an input coupled to the control signal input and an output coupled to ground; and 
 
 an AND gate comprising a first input coupled to the input of the first capacitor, a second input coupled to the input of the second capacitor, and an output configured for coupling to an integrated circuit to control the integrated circuit to reset; and 
 a switch configured for manually resetting the integrated circuit, a first end of the switch is coupled to the junction of the first resistor and the first capacitor, and a second end is coupled to ground. 
 
     
     
       7. The time delay circuit as claimed in  claim 6 , wherein charging times of the first capacitor and the second capacitor are greater than a rest time of the integrated circuit. 
     
     
       8. The time delay circuit as claimed in  claim 6 , wherein the control signal input is configured for coupling to a watchdog chip, the watchdog chip configured for detecting running errors of the integrated circuit, and sending a reset signal to the control signal input so as to provide a low level signal to the second input of the AND gate, such that the AND gate outputs a low level signal to reset the integrated circuit. 
     
     
       9. The time delay circuit as claimed in  claim 8 , wherein the reset signal is a low signal input. 
     
     
       10. The time delay circuit as claim in  claim 8 , wherein the low signal input and the low level signal are about 0 volts. 
     
     
       11. The time delay circuit as claimed in  claim 6 , wherein the switch is a depress type switch.