Low power serdes architecture using serial I/O burst gating

Abstract

A serializer/deserializer is disclosed with a flexible design that allows for sending data streams between computer systems where the power dissipation is markedly reduced by placing the serializer/deserializer in a standby, low power mode between the sending of data. Word data bits are framed and sent along with clock pulses that define when the bits may be reliably received. High speed, typically, CML logic is used for the transmission line drivers and together with the clock pulse, a data word is sent faster than the computer system can send the next word to the serializer/deserializer. The disclosure frames the word and detects the word end, whereupon the system is placed into the standby mode. In addition the serializer/deserializers may be placed in a master/slave arrangement where the slave can be arranged to use the master's clock to send word data bits back to the master.

1. A serializer comprising:
 an oscillator outputting clock pulses, 
 logic circuitry that accepts data words comprised of data bits received from a system connected to the serializer; 
 word boundary logic circuitry that frames the data bits with framing bits; 
 
     wherein the oscillator runs and presents the framed data bits serially to a driver, wherein the driver accepts each frame and data bit and drives a transmission line, wherein the driver defines a low power standby mode and a high power burst mode; and wherein only when a framed data word is being sent the driver is placed into the high power burst mode; and wherein the framed data word is sent faster than the system outputs successive data words;
 a controller that determines when the framed word has been sent and then places the driver into the low power standby mode. 
 
   
   
     2. The serializer of  claim 1  wherein the oscillator is stopped when the driver is placed in the standby mode. 
   
   
     3. The serializer of  claim 1  wherein the driver is a differential current logic driver. 
   
   
     4. The serializer of  claim 3  wherein the driver comprising a CMOS logic to differential current logic converter that converts a single ended logic signal to a differential signal. 
   
   
     5. The serializer of  claim 3  wherein the differential current logic driver comprises two NMOSs with common sources stacked below two PMOSs with common drains, wherein the drain of each NMOS is tied to the source of one PMOS, and where the gate of the NMOS and the gate of the PMOS whose source connects to the NMOS drain are tied together and tied to one of the outputs of the CMOS logic to differential logic converter, and where the gates of the remaining NMOS and PMOS are tied together and to the other output of the CMOS logic to differential logic converter, and wherein the drains of the PMOS are connected to at least one current source that is enabled when in the high power burst mode and disabled when in the low power standby mode. 
   
   
     6. The serializer of  claim 1  further comprising:
 logic circuitry that accepts control data from the system connected to the serializer. 
 
   
   
     7. The serializer of  claim 1  wherein the transmission line comprises two transmission lines, one carrying word data bits and the other carrying clock pulses, and further comprising a second driver that outputs a clock pulse when the driver outputs a word data bit, wherein the clock pulse indicates when the word data bit may be received. 
   
   
     8. A serializer/deserializer comprising a serializer of  claim 1  and further comprising a deserializer, the deserializer comprising
 a receiver connected to the distal end of the transmission line; 
 logic circuitry that accepts each bit from the transmission line; 
 deserializing circuitry that takes each bit from the logic circuitry, detects the word boundary and present the received data word to a system connected to the deserializer; and 
 control circuitry that conditions the deserializer to respond to control signals. 
 
   
   
     9. A serializer/deserializer system as in  claim 8  further comprising a second serializer/deserializer as in  claim 8 , the second serializer/deserializer comprising a deserializer at the adjacent end of the transmission line and a serializer at the distal end of the transmission line. 
   
   
     10. The serializer/deserializer of  claim 9  wherein the serializer and the deserializer at the adjacent or at the distal end of the transmission line can either can send or receive data on the transmission line. 
   
   
     11. The serializer/deserializer of  claim 9  wherein the serializer and deserializer at the adjacent end of the transmission line comprise a master and the serializer and deserializer at the distal end of the transmission line comprise a slave, and wherein the transmission line comprises two differential pairs, one pair carrying serial word data bits and the other pair carrying timing pulses. 
   
   
     12. The serializer/deserializer of  claim 11  wherein the master can send control information to the slave. 
   
   
     13. The serializer/deserializer of  claim 12  wherein the master can control the slave to use the clock signal received from the master and use that clock to place the word data bits onto the word data carrying transmission line. 
   
   
     14. A method for serializing data, the method comprising the steps of:
 outputting clock pulses, 
 accepting data words comprised of data bits in from a system connected to the serializer; 
 framing the data word, wherein the framing comprises framing bits; 
 outputting a framing or a data bit with each clock pulse, wherein the clock pulses are arranged to output a framed data word faster than the system outputs successive data words; 
 driving a transmission line with each framing or data bit, wherein the driver defines a low power standby mode when not driving the transmission line and a high power burst mode when driving the transmission line; and 
 determining that the framed data word has been sent, and then placing the driver into the low power standby mode. 
 
   
   
     15. The method of  claim 14  further comprising the step of stopping the oscillator when the driver is placed in the standby mode. 
   
   
     16. The method of  claim 14  wherein the step of driving the transmission line comprises the steps of differentially current driving the transmission line. 
   
   
     17. The method of  claim 16  wherein the step of driving comprises the step of converting single ended CMOS logic signals to differential current logic signals suitable for driving a differential transmission line pair. 
   
   
     18. The method of  claim 14  further comprising:
 sending control information from the system connected to the serializer. 
 
   
   
     19. The method for serializing of  claim 18  further comprising the steps of
 sending serial data from the distal end of the transmission line to the adjacent end, and 
 receiving the serial data from the distal end and deserializing the data at the adjacent end of the transmission line. 
 
   
   
     20. The method of  claim 19  wherein the serializer or the deserializer at the adjacent or at the distal end of the transmission line can either can send or receive on the transmission line. 
   
   
     21. The method of  claim 19  further comprising the steps of:
 arranging in the serializer and deserializer at the adjacent end of the transmission line to be a master; and 
 arranging the serializer and deserializer at the distal end of the transmission line to be a slave, and wherein the transmission line comprises two differential pairs, one pair carrying serial word data bits and the other pair carrying timing pulses. 
 
   
   
     22. The method of  claim 21  further comprising the step of the master sending control information to the slave. 
   
   
     23. The method of  claim 22  further comprising the master sending control information to the slave, wherein the slave receives the clock signal from the master and uses that clock for placing the word data bits onto the word data carrying transmission line, and sending that clock back to the master on the clock carrying transmission line. 
   
   
     24. The method of  claim 14  further comprising the steps of sending data word bits on one transmission line pair and sending clock pulses on wherein the transmission line comprises two transmission lines, one carrying word data bits and the other carrying clock pulses, and further comprising a second driver that accepts the clock pulses and outputs a clock pulse when the driver outputs a word data bit, wherein the clock pulse indicates when the word data bit may be received. 
   
   
     25. A method for serializing and deserializing data, the method comprising the method of  claim 14  and further comprising the steps of:
 receiving control information to programming a system at the distal end of the transmission line to receive serial data bits; 
 receiving the serial data bits; 
 deserializing the word data bits; 
 detecting word boundaries and presenting the received data word to a system connected to the deserializer.