Semiconductor memory and method for manufacturing the same

Abstract

A capacitor of a semiconductor memory of the present invention includes: a lower electrode which covers the surface of a storage node hole from the bottom to at least one of the sidewalls up to a level lower than the top surface of a second interlayer insulating film; a capacitive insulating film which covers the lower electrode; and an upper electrode which covers the capacitive insulating film.

1. A semiconductor memory comprising:
 a first interlayer insulating film formed on a silicon substrate having an impurity diffusion layer; 
 a capacitor contact formed to penetrate the first interlayer insulating film and connected to the impurity diffusion layer; 
 a second interlayer insulating film formed on the first interlayer insulating film; 
 a trench formed to penetrate the second interlayer insulating film and connected to the capacitor contact; 
 a lower electrode formed only in the trench and connected to the capacitor contact; 
 a capacitive insulating film directly formed on the lower electrode; 
 an upper electrode formed on the capacitive insulating film; and 
 a third interlayer insulating film formed on the upper electrode; 
 wherein the lower electrode is not formed in an upper region of side surfaces of the second interlayer insulating film in the trench, 
 the capacitive insulating film is formed directly on the upper region of side surfaces of the second interlayer insulating film, and 
 the capacitive insulating film and the upper electrode extend from a side surface of the second interlayer insulating film within the trench onto a top surface of the second interlayer insulating film, and 
 said third interlayer insulating film is buried in the trench with the upper electrode interposed therebetween. 
 
     
     
       2. A semiconductor memory according to  claim 1 , wherein the upper end of the lower electrode is positioned lower than the top surface of the second interlayer insulating film by a distance which is 0.3 or more times larger than the thickness of the upper electrode. 
     
     
       3. A semiconductor memory according to  claim 1 , wherein the lower electrode comprises a single layer film. 
     
     
       4. A semiconductor memory according to  claim 3 , wherein the single layer film is a TiN film. 
     
     
       5. A semiconductor memory according to  claim 1 , wherein the upper electrode comprises a single layer film. 
     
     
       6. A semiconductor memory according to  claim 1 , wherein the capacitive insulating film is made of a Ta 2 O 5  film. 
     
     
       7. A semiconductor memory according to  claim 1 , further comprising:
 a bit line contact formed to penetrate the second interlayer insulating film, 
 wherein the upper electrode includes on the top surface of the second interlayer insulating film, an opening surrounding the bit line contact and having an edge apart from the bit line contact. 
 
     
     
       8. A semiconductor memory according to  claim 1 , wherein the lower electrode is formed on a sidewall of the trench, in a region 50 nm or more away from the top surface of the second interlayer insulating film. 
     
     
       9. A semiconductor memory comprising:
 a first interlayer insulating film formed on a silicon substrate having an impurity diffusion layer; 
 a capacitor contact formed to penetrate the first interlayer insulating film and connected to the impurity diffusion layer; 
 a second interlayer insulating film formed on the first interlayer insulating film; 
 an insulating film formed on the second interlayer insulating film and having an etch rate different from the second interlayer insulating film; 
 a trench formed to penetrate the second interlayer insulating film and the insulating film and connected to the capacitor contact; 
 a lower electrode formed only in the trench and connected to the capacitor contact; 
 a capacitive insulating film directly formed on the lower electrode; 
 an upper electrode formed on the capacitive insulating film; and 
 a third interlayer insulating film formed on the upper electrode; 
 wherein the lower electrode is not formed on side surfaces of the insulating film in the trench, 
 the capacitive insulating film is formed directly on side surfaces of the insulating film, and 
 the capacitive insulating film and the upper electrode extend from a side surface of the second interlayer insulating film within the trench onto a top surface of the second interlayer insulating film, and 
 said third interlayer insulating film is buried in the trench with the upper electrode interposed therebetween. 
 
     
     
       10. A semiconductor memory according to  claim 9 , wherein the upper end of the lower electrode is thinner than the other part of the lower electrode. 
     
     
       11. A semiconductor memory according to  claim 9 , wherein the insulating film protrudes toward the inside of the trench beyond the second interlayer insulating film by a length larger than the difference in thickness between the lower electrode and the capacitive insulating film. 
     
     
       12. A semiconductor memory according to  claim 9 , wherein the second interlayer insulating film is made of phospho-silicate glass and the insulating film is made of non-doped silicate glass. 
     
     
       13. A semiconductor memory according to  claim 5 , wherein the single layer film is a TiN film. 
     
     
       14. A semiconductor memory according to  claim 9 , wherein in the trench, the insulating film overhangs the second interlayer insulating film. 
     
     
       15. A semiconductor memory according to  claim 9 , wherein the lower electrode comprises a single layer film. 
     
     
       16. A semiconductor memory according to  claim 15 , wherein the single layer film is a TiN film. 
     
     
       17. A semiconductor memory according to  claim 9 , wherein the upper electrode comprises a single layer film. 
     
     
       18. A semiconductor memory according to  claim 17 , wherein the single layer film is a TiN film. 
     
     
       19. A semiconductor memory according to  claim 9 , wherein the capacitive insulating film is made of a Ta 2 O 5  film. 
     
     
       20. A semiconductor memory according to  claim 9 , further comprising:
 a bit line contact formed to penetrate the second interlayer insulating film, 
 wherein the upper electrode includes on the top surface of the second interlayer insulating film, an opening surrounding the bit line contact and having an edge apart from the bit line contact.