Complementary metal oxide semiconductor device with an electroplated metal replacement gate

Abstract

Disclosed herein are embodiments of a method of forming a complementary metal oxide semiconductor (CMOS) device that has at least one high aspect ratio gate structure with a void-free and seam-free metal gate conductor layer positioned on top of a relatively thin high-k gate dielectric layer. These method embodiments incorporate a gate replacement strategy that uses an electroplating process to fill, from the bottom upward, a high-aspect ratio gate stack opening with a metal gate conductor layer. The source of electrons for the electroplating process is a current passed directly through the back side of the substrate. This eliminates the need for a seed layer and ensures that the metal gate conductor layer will be formed without voids or seams. Furthermore, depending upon the embodiment, the electroplating process is performed under illumination to enhance electron flow to a given area (i.e., to enhance plating) or in darkness to prevent electron flow to a given area (i.e., to prevent plating).

1. A method of forming a semiconductor device, said method comprising:
 providing a p-type substrate, having a first section and a second section positioned laterally adjacent to said first section; 
 forming an n-type well region in said first section; 
 forming a first gate stack on said first section and a second gate stack on said second section, wherein said forming of said first gate stack and said second gate stack comprises:
 forming a dielectric layer adjacent to said substrate; 
 forming an n-type metal layer adjacent to said dielectric layer; 
 forming a polysilicon layer adjacent to said n-type metal layer; and 
 patterning and etching said polysilicon layer, said n-type metal layer and said polysilicon layer so as to form said first gate stack and said second gate stack; and 
 
 removing said polysilicon layer and said n-type metal layer from said first gate stack; and 
 electroplating a p-type metal layer on said dielectric layer of said first gate stack, wherein said electroplating is performed with a current applied to said substrate and under illumination so as to ensure electron flow through said substrate and said n-type well region to said first gate stack. 
 
   
   
     2. The method according to  claim 1 , all the limitations of which are incorporated by reference, wherein said first gate stack and said second gate stack are formed such that said dielectric layer comprises a high-k dielectric layer. 
   
   
     3. The method according to  claim 1 , all the limitations of which are incorporated by reference, wherein said electroplating is performed without a seed layer such that said p-type metal layer is electroplated from said dielectric layer up without voids and seams and such that said p-type metal layer is in direct contact with said dielectric layer and with adjacent to sidewall spacers. 
   
   
     4. The method according to  claim 1 , all the limitations of which are incorporated by reference, further comprising, before said removing, forming first source/drain regions for a p-type transistor in said first section and second source/drain regions for an n-type transistor in said second section. 
   
   
     5. The method according to  claim 1 , all the limitations of which are incorporated by reference, wherein said first gate stack and said second gate stack are formed with a width-to-height ratio of one to at least five. 
   
   
     6. A method of forming a semiconductor device, said method comprising:
 providing a p-type substrate, having a first section and a second section positioned laterally adjacent to said first section; 
 forming an n-type well region in said first section; 
 forming a first gate stack on said first section and a second gate stack on said second section, wherein said forming of said first gate stack and said second gate stack comprises:
 forming a dielectric layer adjacent to said substrate; 
 forming an n-type metal layer adjacent to said dielectric layer; 
 forming a polysilicon layer adjacent to said n-type metal layer; and 
 patterning and etching said polysilicon layer, said n-type metal layer and said polysilicon layer to form said first gate stack and said second gate stack; 
 
 forming sidewall spacers adjacent to opposing sidewalls of said first gate stack and said second gate stack; 
 removing said polysilicon layer and said n-type metal layer from said first gate stack; 
 electroplating a p-type metal layer on said dielectric layer of said first gate stack, wherein said electroplating is performed with a current applied to said substrate and under illumination so as to ensure electron flow through said substrate and said n-type well region to said first gate stack; and 
 after said electroplating, filling, with a wiring metal layer, a space above said p-type metal layer between said sidewall spacers of said first gate stack. 
 
   
   
     7. The method according to  claim 6 , all the limitations of which are incorporated by reference, wherein said first gate stack and said second gate stack are formed such that said dielectric layer comprises a high-k dielectric layer. 
   
   
     8. The method according to  claim 6 , all the limitations of which are incorporated by reference, wherein said electroplating is performed without a seed layer such that said p-type metal layer is electroplated from said dielectric layer up without voids and seams and such that said p-type metal layer is in direct contact with said dielectric layer and said sidewall spacers. 
   
   
     9. The method according to  claim 6 , all the limitations of which are incorporated by reference, further comprising, before said removing, forming first source/drain regions for a p-type transistor in said first section and second source/drain regions for an n-type transistor in said second section. 
   
   
     10. The method according to  claim 6 , all the limitations of which are incorporated by reference, wherein said first gate stack and said second gate stack are formed with a width-to-height ratio of one to at least five. 
   
   
     11. A method of forming a semiconductor device, said method comprising:
 providing a p-type substrate, having a first section and a second section positioned laterally adjacent to said first section; 
 forming an n-type well region in said first section; 
 forming a first gate stack on said first section and a second gate stack on said second section, wherein said forming of said first gate stack and said second gate stack comprises:
 forming a dielectric layer adjacent to said substrate; 
 forming a polysilicon layer adjacent to said dielectric layer; and 
 patterning and etching said polysilicon layer and said dielectric layer to form said first gate stack and said second gate stack; 
 
 forming sidewall spacers adjacent to opposing sidewalls of said first gate stack and said second gate stack; 
 removing said polysilicon layer from said first gate stack and said second gate stack; 
 masking said second gate stack and electroplating a p-type metal layer on said dielectric layer of said first gate stack, wherein said electroplating of said p-type metal layer is performed with a current applied to said substrate and under illumination so as to ensure electron flow through said substrate and said n-type well region to said first gate stack; and 
 masking said first gate stack and electroplating an n-type metal layer on said dielectric layer of said second gate stack. 
 
   
   
     12. The method according to  claim 11 , all the limitations of which are incorporated by reference, wherein said first gate stack and said second gate stack are formed such that said dielectric layer comprises a high-k dielectric layer. 
   
   
     13. The method according to  claim 11 , all the limitations of which are incorporated by reference, wherein said electroplating of said p-type metal layer and said electroplating of said n-type metal layer are performed without seed layers such that said p-type metal layer is electroplated from said dielectric layer of said first gate stack up without voids and seams and such that said n-type metal layer is electroplated from said dielectric layer of said second gate stack up without voids and seams. 
   
   
     14. The method according to  claim 11 , all the limitations of which are incorporated by reference, further comprising, after said electroplating of said p-type metal layer and said electroplating of said n-type metal layer, filling, with a wiring metal layer, spaces above said p-type metal layer between said sidewall spacers of said first gate stack and above said n-type metal layer between said sidewall spacers of said second gate stack. 
   
   
     15. The method according to  claim 11 , all the limitations of which are incorporated by reference, further comprising, before said removing, forming first source/drain regions for a p-type transistor in said first section and second source/drain regions for an n-type transistor in said second section. 
   
   
     16. The method according to  claim 11 , all the limitations of which are incorporated by reference, wherein said first gate stack and said second gate stack are formed with a width-to-height ratio of one to at least five. 
   
   
     17. A method of forming a semiconductor device, said method comprising:
 providing an n-type substrate, having a first section and a second section positioned laterally adjacent to said first section; 
 forming a p-type well region in said second section; 
 forming a first gate stack on said first section and a second gate stack on said second section, wherein said forming of said first gate stack and said second gate stack comprises:
 forming a dielectric layer adjacent to said substrate; 
 forming a polysilicon layer adjacent to dielectric layer; and 
 patterning and etching said polysilicon layer and said dielectric layer to form said first gate stack and said second gate stack; 
 
 forming sidewall spacers adjacent to opposing sidewalls of said first gate stack and said second gate stack; 
 removing said polysilicon layer from said first gate stack and said second gate stack; 
 selectively electroplating a p-type metal layer on said dielectric layer of said first gate stack, wherein said selectively electroplating of said p-type metal layer is performed with a current applied to said substrate and in darkness so as to allow electron flow through said substrate to said first gate stack and to prevent electron flow through said p-type well region to said second gate stack; and 
 after said selectively electroplating of said p-type metal layer, electroplating an n-type metal layer on said p-type metal layer of said first gate stack and on said dielectric layer of said second gate stack, wherein said electroplating of said n-type metal layer is performed under illumination so as to ensure electron flow through said substrate and said p-type well region to said second gate stack. 
 
   
   
     18. The method according to  claim 17 , all the limitations of which are incorporated by reference, wherein said first gate stack and said second gate stack are formed such that said dielectric layer comprises a high-k dielectric layer. 
   
   
     19. The method according to  claim 17 , all the limitations of which are incorporated by reference, wherein said electroplating of said p-type metal layer and said electroplating of said n-type metal layer are performed without seed layers such that said p-type metal layer is electroplated from said dielectric layer of said first gate stack up without voids and seams and such that said n-type metal layer is electroplated from said p-type metal layer of said first gate stack and from said dielectric layer of said second gate stack up without voids and seams. 
   
   
     20. The method according to  claim 17 , all the limitations of which are incorporated by reference, further comprising, before said removing, forming first source/drain regions for a p-type transistor in said first section and second source/drain regions for an n-type transistor in said second section. 
   
   
     21. The method according to  claim 17 , all the limitations of which are incorporated by reference, wherein said first gate stack and said second gate stack are formed with a width-to-height ratio of one to at least five. 
   
   
     22. A method of forming a semiconductor device, said method comprising:
 providing an n-type substrate, having a first section and a second section positioned laterally adjacent to said first section; 
 forming a p-type well region in said second section; 
 forming a first gate stack on said first section and a second gate stack on said second section, wherein said forming of said first gate stack and said second gate stack comprises:
 forming a dielectric layer adjacent to said substrate; 
 forming a polysilicon layer adjacent to dielectric layer; and 
 patterning and etching said polysilicon layer and said dielectric layer to form said first gate stack and said second gate stack; 
 
 forming sidewall spacers adjacent to opposing sidewalls of said first gate stack and said second gate stack; 
 removing said polysilicon layer from said first gate stack and said second gate stack; 
 selectively electroplating a p-type metal layer on said dielectric layer of said first gate stack, wherein said selectively electroplating of said p-type metal layer is performed with a current applied to said substrate and in darkness so as to allow electron flow through said substrate to said first gate stack and to prevent electron flow through said p-type well region to said second gate stack; and 
 after said selectively electroplating of said p-type metal layer, electroplating an n-type metal layer on said p-type metal layer of said first gate stack and on said dielectric layer of said second gate stack so as to fill a space between said sidewalls spacers of said first gate stack and said second gate stack, wherein said electroplating of said n-type metal layer is performed under illumination so as to ensure electron flow through said substrate and said p-type well region to said second gate stack. 
 
   
   
     23. The method according to  claim 22 , all the limitations of which are incorporated by reference, wherein said first gate stack and said second gate stack are formed such that said dielectric layer comprises a high-k dielectric layer. 
   
   
     24. The method according to  claim 22 , all the limitations of which are incorporated by reference, wherein said electroplating of said p-type metal layer and said electroplating of said n-type metal layer are performed without seed layers such that said p-type metal layer is electroplated from said dielectric layer of said first gate stack up without voids and seams and such that said n-type metal layer is electroplated from said p-type metal layer of said first gate stack and from said dielectric layer of said second gate stack up without voids and seams. 
   
   
     25. The method according to  claim 22 , all the limitations of which are incorporated by reference, wherein said first gate stack and said second gate stack are formed with a width-to-height ratio of one to at least five.