P
US7776707B2ExpiredUtilityPatentIndex 63

Method for manufacturing dielectric memory

Assignee: PANASONIC CORPPriority: Jun 7, 2006Filed: Jun 5, 2007Granted: Aug 17, 2010
Est. expiryJun 7, 2026(expired)· nominal 20-yr term from priority
Inventors:YOSHIDA HIROSHIITO TOYOJINAGANO YOSHIHISA
H10D 1/694H10D 1/682H10B 53/00H10B 53/30
63
PatentIndex Score
2
Cited by
3
References
8
Claims

Abstract

A method includes the steps of: forming a first insulation film on a substrate; forming a hole in the first insulation film; forming a lower electrode on a bottom surface and a sidewall surface of the hole; forming a capacitor insulation film on the lower electrode; forming a second conductive layer on the capacitor insulation film; forming a second insulation film on the second conductive layer so that the second insulation film fills a recess corresponding to the hole; forming a resist mask on the second insulation film so that the resist mask covers the recess; patterning the second insulation film by using the resist mask; and patterning the second conductive layer and the capacitor insulation film by using the patterned second insulation film as a hard mask. By dry etching using a hard mask, a dielectric capacitor having a three-dimensionally stacked structure can be formed with a high yield.

Claims

exact text as granted — not AI-modified
1. A method for manufacturing a dielectric memory, comprising the steps of:
 forming a first insulation film on a substrate; 
 forming a hole in the first insulation film; 
 forming a first conductive layer on a bottom surface and a sidewall surface of the hole; 
 forming a dielectric layer on the first conductive layer; 
 forming a second conductive layer on the dielectric layer; 
 forming a second insulation film on the second conductive layer so that the second insulation film fills a recess corresponding to the hole; 
 forming a resist mask on the second insulation film so that the resist mask covers the recess; 
 patterning the second insulation film by using the resist mask; and 
 patterning the second conductive layer and the dielectric layer by using the patterned second insulation film as a hard mask, 
 wherein in the step of forming the second insulation film, an opening of the recess is closed with the second insulation film at a level above an upper surface of the second conductive layer, thereby forming a void within the recess. 
 
     
     
       2. The method according to  claim 1 , wherein a sum of a film thickness of the second insulation film formed on the bottom inside the recess and a film thickness of the second insulation film formed in an upper part inside the recess is greater than a film thickness of the second insulation film outside the recess. 
     
     
       3. The method according to  claim 1 , wherein the first conductive layer and the second conductive layer are formed with noble metal materials. 
     
     
       4. The method according to  claim 3 , wherein Pt, Ir, or Ru is used in the noble metal materials. 
     
     
       5. The method according to  claim 1 , further comprising the step of:
 forming a nitride film or an oxide film containing Ti or Al between the second conductive layer and the second insulation film. 
 
     
     
       6. The method according to  claim 1 , wherein the second insulation film is a silicon oxide film or a silicon nitride film. 
     
     
       7. The method according to  claim 1 , further comprising the step of:
 flattening the second insulation film by chemical mechanical polishing after the second insulation film is formed. 
 
     
     
       8. The method according to  claim 1 , further comprising the step of:
 forming a third insulation film on the substrate so that the third insulation film covers the second insulation film, after the step of patterning the dielectric layer.

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