Symmetrical clock distribution in multi-stage high speed data conversion circuits

Abstract

Provided is a high speed bit stream data conversion circuit that includes input ports to receive first bit streams at a first bit rate. Data conversion circuits receive the first bit streams and produce second bit stream(s), wherein the number and bit rate of the first and second bit stream(s) differ. Symmetrical pathways transport the first bit streams from the input ports to the data conversion circuits, wherein their transmission time(s) are substantially equal. A clock distribution circuit receives and symmetrically distributes a clock signal to data conversion circuits. A central trunk coupled to the clock port and located between a first pair of circuit pathways with paired branches that extend from the trunk and that couple to the data conversion circuits make up the clock distribution circuit. The distributed data clock signal latches data in data conversion circuits from the first to the second bit stream(s).

1. A high speed bit stream data conversion circuit comprising:
 a plurality of data conversion circuits that receive a first plurality of bit streams at a first bit rate and that produce at least one second bit stream at a second bit rate, wherein a number and the bit rate of the first plurality of bit streams and the at least one second bit stream differ; 
 a plurality of symmetrical data circuit pathways that include pairs of circuit pathways, and that transport the first plurality of bit streams to the plurality of data conversion circuits, wherein transmission times for the first plurality of bit streams on the plurality of symmetrical data circuit pathways are substantially equal; 
 a clock distribution circuit that receives a data clock signal and symmetrically distributes the data clock signal to the plurality of data conversion circuits along a plurality of symmetrical clock circuit pathways, wherein the symmetrical clock circuit pathways further include a central trunk located between a first pair of circuit pathways, and symmetrical pairs of branches that extend from the central trunk and couple to the plurality of data conversion circuits, and wherein clock transmission times associated with each symmetrical clock circuit pathway are substantially equal, and wherein the distributed data clock signal latches data in the plurality of data conversion circuits from the first plurality of bit streams to the at least one second bit stream at the second bit rate, and wherein the pairs of circuit pathways include a first pathway located on a first side of the central trunk and a second pathway located on a second side of the central trunk, wherein the second side is opposite the first side. 
 
   
   
     2. The high speed bit stream data conversion circuit of  claim 1 , wherein the clock distribution circuit further comprises a plurality of delay elements operable to compensate for skewing of the data clock signal received by each data conversion circuit. 
   
   
     3. The high speed bit stream data conversion circuit of  claim 2 , wherein each of the delay elements comprise switched capacitor networks that introduce delay increments based on a capacitance coupled to a buffer amplifier. 
   
   
     4. The high speed bit stream data conversion circuit of  claim 3 , wherein the capacitance coupled to the buffer amplifier is a variable capacitance. 
   
   
     5. The high speed bit stream data conversion circuit of  claim 4 , wherein the variable capacitance will increase or decrease the buffer amplifier delay time. 
   
   
     6. The high speed bit stream data conversion circuit of  claim 2 , wherein each symmetrical data circuit pathway that transports the first plurality of bit streams further comprises a retimer that ensures data integrity between the first plurality of bit streams and the at least one second bit stream. 
   
   
     7. The high speed bit stream data conversion circuit of  claim 6 , wherein each of the plurality of data conversion circuits comprises a multiplexer, wherein a number of first bit streams exceeds a number of second bit streams, and wherein the second bit rate exceeds the first bit rate. 
   
   
     8. The high speed bit stream data conversion circuit of  claim 7 , wherein the plurality of first bit streams include 4 bit streams at a bit rate of about 10 GBPS, and wherein the at least one second bit stream include 1 bit stream at a bit rate of about 40 GBPS. 
   
   
     9. The high speed bit stream data conversion circuit of  claim 7 , wherein the first plurality of bit streams include 16 bit streams at a bit rate of about 2.5 GBPS, and wherein the at least one second bit streams include 4 bit stream at about 10 GBPS. 
   
   
     10. The high speed bit stream data conversion circuit of  claim 1 , wherein the plurality of symmetrical data circuit pathways that transport the first plurality of bit streams are symmetrical with respect to the symmetrical clock circuit pathways. 
   
   
     11. The high speed bit stream data conversion circuit of  claim 1 , wherein a physical length of each symmetrical data circuit pathways is substantially equal, and wherein a physical length of each symmetrical clock circuit pathway is substantially equal. 
   
   
     12. A method of converting high speed data bit streams from a first bit rate to a second bit rate, wherein the first and second bit rate differ, comprising:
 receiving a first plurality of bit streams at a first plurality of input ports; 
 distributing the first plurality of bit streams to a plurality of data conversion circuits along a plurality of symmetrically-situated circuit pathways; 
 symmetrically distributing a clock signal to the plurality of data conversion circuits along a plurality of symmetrically-situated clock circuit pathways, wherein clock transmission times associated with each clock circuit pathway are substantially equal, and wherein the symmetrically-situated data circuit pathways are symmetrically-situated relative to the symmetrically-situated clock circuit pathways; and 
 latching data at the plurality of data conversion circuits from the first plurality of bit streams with the distributed clock signal to produce a second bit stream. 
 
   
   
     13. The method of  claim 12 , further comprising:
 delaying the distributed clock signal within individual symmetrically-situated clock circuit pathways to compensate for skewing of the data clock signal received by each data conversion circuit; and 
 retiming data at the individual data conversion circuits to compensate for skewing of data within the first bit streams received by each data conversion circuit. 
 
   
   
     14. The method of  claim 13 , wherein delaying the distributed clock signal further comprises introducing delay elements with switched capacitor networks. 
   
   
     15. The method of  claim 14 , wherein the switched capacitor networks provide a controlled variable capacitance. 
   
   
     16. The method of  claim 15 , wherein each of the plurality of data conversion circuits comprise a multiplexer, wherein a number of first bit streams exceeds a number of second bit streams, and wherein the second data rate exceeds the first data rate. 
   
   
     17. The method of  claim 16 , wherein the first bit streams include 4 bit streams at about 10 GBPS, and wherein the second bit streams include 1 bit stream at about 40 GBPS. 
   
   
     18. The method of  claim 16 , wherein the first bit streams include 16 bit streams at about 2.5 GBPS, and wherein the second bit streams include 4 bit streams at about 10 GBPS. 
   
   
     19. The method of  claim 16 , wherein a physical length of each symmetrically-situated data circuit pathway is substantially equal, and wherein a physical length of each symmetrically-situated clock circuit pathway is substantially equal. 
   
   
     20. The method of  claim 13 , wherein the retiming data further comprises introducing delay elements with switched capacitor networks.