Method for fabricating photo sensor

Abstract

A method for fabricating a photo sensor on an amorphous silicon thin film transistor panel includes forming a photo sensor with a bottom electrode, a silicon-rich dielectric layer, and a top electrode, such that the light sensor has a high reliability. The fabrication method is compatible with the fabrication process of a thin film transistor.

1. A method of fabricating a photo sensor on an amorphous silicon TFT panel, comprising:
 providing a substrate comprising a TFT region and a sensor region; 
 forming a first patterned conductive layer on the substrate, the first patterned conductive layer comprising a gate electrode of a TFT disposed in the TFT region; 
 forming a gate insulating layer on the substrate and the gate electrode; 
 forming a patterned amorphous silicon layer on the gate insulating layer corresponding to the gate electrode; 
 forming a second patterned conductive layer on the substrate, wherein the second patterned conductive layer comprises a source electrode, a drain electrode and a bottom electrode of a photo sensor, the source electrode and the drain electrode are disposed above the gate electrode, and the bottom electrode is disposed in the sensor region; 
 forming a patterned silicon-rich dielectric layer on the substrate, the patterned silicon-rich dielectric layer comprising being disposed in the sensor region and electrically connected to the bottom electrode, and the patterned silicon-rich dielectric layer at least partially exposing the drain electrode; and 
 forming a patterned transparent conductive layer on the substrate, the patterned transparent conductive layer at least comprising a top electrode disposed in the sensor region. 
 
     
     
       2. The method of  claim 1 , wherein the patterned silicon-rich dielectric layer comprises a compound of silicon, oxygen, nitrogen, carbon, or hydrogen. 
     
     
       3. The method of  claim 1 , wherein a molecular formula of the patterned silicon-rich dielectric layer comprises SiOC, SiC, SiOx, SiNx, SiONy, SiOH, or a mixture thereof. 
     
     
       4. The method of  claim 1 , wherein forming the patterned silicon-rich dielectric layer comprising:
 forming a silicon-rich dielectric layer on the substrate, wherein forming the silicon-rich dielectric layer comprises performing a chemical vapor deposition process; and 
 subsequently performing a photolithographic and etching process to pattern the silicon-rich dielectric layer. 
 
     
     
       5. The method of  claim 4 , comprising introducing a gas comprising silicon, oxygen, nitrogen, carbon, hydrogen, or a mixture thereof in the chemical vapor deposition process. 
     
     
       6. The method of  claim 1 , wherein the patterned silicon-rich dielectric layer partially covers the source electrode and the drain electrode. 
     
     
       7. The method of  claim 1 , further comprising forming a patterned passivation layer on the substrate covering the TFT and partially exposing the drain electrode and the patterned silicon-rich dielectric layer subsequent to forming the patterned silicon-rich dielectric layer. 
     
     
       8. The method of  claim 7 , wherein the patterned passivation layer comprises an organic photoresist material. 
     
     
       9. The method of  claim 8 , wherein forming the patterned passivation layer comprises:
 forming an organic photoresist layer entirely covering the substrate subsequent to forming the patterned silicon-rich dielectric layer; 
 performing an exposure process to define a through hole pattern and an opening pattern in the organic photoresist layer, wherein the through hole pattern is disposed in the TFT region and the opening pattern is disposed in the sensor region; and 
 performing a development process to remove the organic photoresist layer of the through hole pattern and the opening pattern to form the patterned passivation layer. 
 
     
     
       10. The method of  claim 7 , wherein forming the second patterned conductive layer, the patterned silicon-rich dielectric layer, and the patterned passivation layer comprises:
 consecutively forming a second conductive layer and a silicon-rich dielectric layer entirely covering the substrate; 
 partially removing the second conductive layer and the silicon-rich dielectric layer simultaneously to form the second patterned conductive layer, and to make the silicon-rich dielectric layer and the second patterned conductive layer have the same pattern in the sensor region; 
 forming a dielectric layer entirely on the substrate; and 
 performing a photolithographic and etching process using a halftone mask to partially remove the dielectric layer and the silicon-rich dielectric layer simultaneously to form the patterned silicon-rich dielectric layer, and to make the dielectric layer form the patterned passivation layer partially exposing the drain electrode and the patterned silicon-rich dielectric layer. 
 
     
     
       11. The method of  claim 10 , wherein the halftone mask comprises a translucent region, and a portion of the translucent region is corresponding to the silicon-rich dielectric layer or the sensor region. 
     
     
       12. The method of  claim 1 , wherein forming the patterned amorphous silicon layer and the second patterned conductive layer comprises:
 consecutively forming an amorphous silicon layer, a second conductive layer, a silicon-rich dielectric layer and a photoresist layer on the substrate subsequent to forming the gate insulating layer; 
 applying a halftone mask to define patterns of the source electrode, the drain electrode, the bottom electrode and a semiconductor channel of the TFT in the photoresist layer; and 
 performing an etching process using the photoresist layer as an etching mask to partially remove the silicon-rich dielectric layer, the second conductive layer, and the amorphous silicon layer simultaneously, wherein the remaining silicon-rich dielectric layer and the remaining second patterned conductive layer have substantially identical patterns, which partially expose the amorphous silicon layer in the TFT region. 
 
     
     
       13. The method of  claim 12 , wherein the halftone mask comprises a translucent region and an opaque region, the translucent region is corresponding to the semiconductor channel, and the opaque region is corresponding to the drain electrode, the source electrode and the bottom electrode. 
     
     
       14. The method of  claim 1 , further comprising forming a passivation layer on the substrate covering the TFT and partially exposing the drain electrode and the bottom electrode prior to forming the patterned silicon-rich dielectric layer. 
     
     
       15. The method of  claim 1 , further comprising defining the gate electrode, the patterned amorphous silicon layer, the source electrode and the drain electrode, the patterned silicon-rich dielectric layer, and the patterned transparent conductive layer respectively with five masks. 
     
     
       16. The method of  claim 1 , wherein the patterned transparent conductive layer comprises a pixel electrode electrically connected to the drain electrode. 
     
     
       17. The method of  claim 1 , wherein forming the patterned amorphous silicon layer, the second patterned conductive layer and the patterned silicon-rich dielectric layer comprising:
 consecutively forming an amorphous silicon layer, a second conductive layer, and a silicon-rich dielectric layer entirely on the substrate; and 
 performing a photolithographic and etching process to partially remove the amorphous silicon layer, the second conductive layer and the silicon-rich dielectric layer simultaneously to form a semiconductor channel in the TFT region, the source electrode and the drain electrode on the gate electrode, and the bottom electrode and the patterned silicon-rich dielectric layer in the sensor region. 
 
     
     
       18. The method of  claim 17 , wherein prior to forming the patterned transparent conductive layer, the method further comprises:
 consecutively forming a passivation layer and a photoresist layer on the substrate; 
 performing a photolithographic process using a halftone mask to pattern the photoresist layer, wherein the patterned photoresist layer comprises a through hole pattern and an opening pattern; and 
 performing an etching process using the patterned photoresist layer as an etching mask to partially remove the passivation layer and the silicon-rich dielectric layer in the TFT region, and partially remove the passivation layer in the sensor region simultaneously so as to form a through hole in the TFT region and an opening in the sensor region. 
 
     
     
       19. The method of  claim 18 , wherein the halftone mask comprises a translucent region corresponding to the opening pattern, and a transparent region corresponding to the through hole pattern. 
     
     
       20. The method of  claim 18 , further comprising:
 forming a transparent conductive layer entirely covering the substrate; and 
 performing a lift-off process to remove the patterned photoresist layer and the transparent conductive layer disposed on the patterned photoresist layer so as to from the patterned transparent conductive layer. 
 
     
     
       21. The method of  claim 1 , wherein the substrate further comprises a pad region, and the method further comprises:
 forming a bottom pad in the pad region simultaneously when forming the gate electrode; and 
 forming a top pad on the bottom pad simultaneously when forming the patterned transparent conductive layer. 
 
     
     
       22. The method of  claim 1 , wherein the silicon-rich dielectric layer comprises silicon nanocrystalline material. 
     
     
       23. The method of  claim 1 , wherein the bottom electrode comprises metal material.