Adjusting output buffer timing based on drive strength

Abstract

This invention operates to select a drive code for an adjustable drive strength transistor in a drive buffer. The drive code is determined employing a scaled-down drive transistor employing varying drive codes compared with a standard. The thus determined drive code is combined with an offset to generate the drive code for the adjustable strength transistor.

1. A method of setting an adjustable buffer drive strength including the steps of:
 comparing a scaled-down drive transistor having a predetermined relationship to an actual drive transistor to a standard at a plurality of drive strengths; 
 selecting one drive strength upon detection of a predetermined relationship between the scaled-down drive transistor at said one drive strength and said standard; 
 determining an offset drive strength to said one drive strength; 
 combining said one drive strength and said offset drive strength to determine an actual drive strength for the actual drive transistor; and 
 setting the drive strength of the actual drive transistor as said determined actual drive strength. 
 
   
   
     2. The method of  claim 1 , wherein:
 said step of comparing a scaled-down drive transistor to the standard at a plurality of drive strengths includes
 causing a digital code source to select minimal drive for drive transistor; 
 setting a test drive strength to a minimum drive strength, 
 comparing a voltage across a reference resistor driven by said scaled-down drive transistor at a current drive strength with a standard voltage, 
 if a comparison has a first predetermined result, selecting the current drive strength as said one drive strength; or 
 if a comparison has a second predetermined result opposite to the first predetermined result, advancing a the current drive strength to a next sequential drive strength and repeating said comparing until a comparison has a first predetermined result. 
 
 
   
   
     3. The method of  claim 1 , wherein:
 said step of determining an offset drive strength includes receiving a user input specifying the offset drive strength. 
 
   
   
     4. The method of  claim 1 , wherein:
 said step of determining an offset drive strength includes
 classifying the actual drive transistor, and 
 recalling an offset drive strength from a look-up table at an entry corresponding to said classification of the actual drive transistor. 
 
 
   
   
     5. The method of  claim 1 , further comprising:
 performing said steps of comparing, selecting, determining, combining and setting a first time for a P-channel actual drive transistor; and 
 performing said steps of comparing, selecting, determining, combining and setting a second time for an N-channel actual drive transistor. 
 
   
   
     6. A buffer having an adjustable drive strength corresponding to a digital code comprising:
 a standard voltage generator; 
 a comparison voltage generator including a resistor having a predetermined resistance and a scaled-down drive transistor having an adjustable drive strength corresponding to said digital code, said scaled-down transistor having a predetermined relationship to an actual drive transistor; 
 an analog comparator comparing said standard voltage and said comparison voltage; 
 a digital code source; 
 a test controller operable to
 initially cause said digital code source to supply a minimal digital code to said scaled-down drive transistor causing said digital code source to select a minimal drive strength, 
 cause said digital code source to supply a next sequential digital code to said scaled-down drive transistor if said analog comparator indicates a first predetermined comparison result, and 
 select a current digital code to supply said actual drive transistor in said buffer if said analog comparator indicates a second predetermined comparison result opposite to said first predetermined comparison result; and 
 
 an add/subtract unit having a first input receiving said selected current digital code, a second input receiving user input offset data and an output generating a sum of said selected current digital code and said user input offset data controlling the drive strength of the adjustable drive strength buffer. 
 
   
   
     7. The buffer of  claim 6 , wherein:
 said scaled-down drive transistor consists of a P-channel transistor; and 
 said buffer further comprising:
 a second scaled-down transistor consisting of an N-channel transistor, said second scaled-down transistor having a predetermined relationship to a second actual drive transistor, 
 a second analog comparator comparing said standard voltage and said comparison voltage, 
 a second digital code source, and 
 a second test controller operable to
 initially cause said second digital code source to supply the minimal digital code to said scaled-down drive transistor causing said second digital code source to select the minimal drive strength, 
 cause said second digital code source to supply a next sequential digital code to said second scaled-down drive transistor if said second analog comparator indicates said first predetermined comparison result, and 
 select a second current digital code to supply said second actual drive transistor in said buffer if said second analog comparator indicates said second predetermined comparison result; and 
 
 a second add/subtract unit having a first input receiving said second selected current digital code, a second input receiving said user input offset data and an output generating a sum of said second selected current digital code and said user input offset data controlling the drive strength of a second adjustable drive strength buffer.