Method of fabricating array substrate for IPS-mode LCD device has a shorter processing time and low error rate without an increase in fabrication and production costs

Abstract

Provided is an array substrate for an IPS-mode LCD device and method of fabricating the same that prevents a problem referred to as wavy noise. The IPS-mode LCD device and method have a shorter processing time and low error rate without an increase in fabrication and production costs.

1. A method of fabricating an array substrate for an IPS-mode LCD device, comprising:
 forming a gate line, a gate electrode, a first common line, and first and second common electrodes on a substrate having a switching region and a pixel region using a first mask process, wherein the gate electrode extends from the gate line and is formed in the switching region, the first common line is substantially parallel to the gate line, and the first and second common electrodes extend from the first common line into the pixel region; 
 sequentially forming a gate insulating layer, an intrinsic amorphous silicon layer and an impurity-doped amorphous silicon layer on the gate line, the gate electrode, and the first and second common electrodes; 
 forming a common line contact hole in the gate insulating layer, an active layer and an impurity-doped amorphous silicon pattern by patterning the gate insulating layer, the intrinsic amorphous silicon layer and the impurity-doped amorphous silicon layer using a second mask process, wherein the common line contact hole exposes the first common line, the active layer corresponds to the gate electrode on the gate insulating layer and the impurity-doped amorphous silicon pattern has a same shape as the active layer on the active layer; and 
 forming a data line, a source electrode, a drain electrode, a plurality of pixel electrodes and a plurality of third common electrodes on the gate insulating layer, the active layer and the impurity-doped amorphous silicon pattern using a third mask process, wherein the data line crosses the gate line to define the pixel region, the source electrode extends from the data line and contacts the impurity-doped amorphous silicon pattern, and the drain electrode is separated from the source electrode and contacts the impurity-doped amorphous silicon pattern, wherein the plurality of pixel electrodes are separated from each other and substantially parallel to the first and second common electrodes, and each of the plurality of pixel electrodes extends from the drain electrode and each of the plurality of electrodes extends from the drain electrode, and wherein the plurality of third common electrodes contact the first common line through the common line contact hole and are alternately arranged with the plurality of pixel electrodes. 
 
     
     
       2. The method according to  claim 1 , further comprising removing the impurity-doped amorphous silicon pattern between the source and drain electrodes to expose the active layer. 
     
     
       3. The method according to the  claim 2 , further comprising forming a silicon oxide layer on the active layer exposed between the source and drain electrodes. 
     
     
       4. The method according to the  claim 1 , wherein forming the gate line, the gate electrode, and the first and second common electrodes includes
 forming a first metal layer on the substrate; 
 forming a transparent conductive layer on the first metal layer; and 
 sequentially patterning the transparent conductive layer and the first metal layer. 
 
     
     
       5. The method according to the  claim 4 , further comprising:
 forming a second metal layer between the first metal layer and the transparent conductive layer; and 
 patterning the second metal layer between the step of patterning the transparent conductive layer and the step of forming the first metal layer. 
 
     
     
       6. The method according to  claim 1 , wherein forming the common line contact hole, the active layer and the impurity-doped amorphous silicon pattern includes:
 forming a photoresist (PR) layer on the impurity-doped amorphous silicon layer; 
 providing a mask having a transmissive area, a blocking area and a half-transmissive area over the PR layer; 
 forming a first PR pattern and second PR patterns by exposing and developing the PR layer using the mask, wherein the first PR pattern corresponds to the gate electrode, and the second PR patterns expose the impurity-doped amorphous silicon layer corresponding to a symmetrical portion of the first common line and have a lower height than the first PR pattern; 
 forming the common line contact hole by sequentially removing the impurity-doped amorphous layer exposed between the second PR patterns, the intrinsic amorphous silicon layer, and the gate insulating layer; 
 ashing the first and second PR patterns such that the second PR patterns are removed and the impurity-doped silicon pattern is exposed; 
 forming the active layer and the impurity-doped silicon pattern by sequentially removing the exposed impurity-doped silicon pattern and the intrinsic amorphous silicon layer; and 
 removing the first PR pattern. 
 
     
     
       7. The method according to  claim 1 , further comprising forming a gate pad electrode, a data link line, a data pad electrode, and a second common line, wherein the gate pad electrode is formed at an end of the gate line, the data link line contacts the data line, the data pad electrode extends from the data link line, and the second common line is substantially parallel to the first common line. 
     
     
       8. The method according to  claim 7 , wherein each of the first and second common electrodes is connected to the first and second common lines, and wherein the first and second common lines and the first and second common electrodes surround the pixel region. 
     
     
       9. The method according to  claim 7 , wherein the drain electrode overlaps the second common line such that the second common line, the drain electrode and the gate insulating layer interposed between the second common line and the drain electrode form a storage capacitor. 
     
     
       10. The method according to  claim 7 , wherein the second mask process includes forming a data link line contact hole exposing an end of the data link line, a gate pad contact hole exposing the gate pad electrode and a data pad contact hole exposing the data pad electrode. 
     
     
       11. The method according to  claim 1 , wherein the source and drain electrodes cover both ends of the semiconductor layer.