Mixer/DAC chip and method

Abstract

An electronic chip has a data input for receiving an input digital data signal with a data frequency, a plurality of switches, and a logic circuit operatively coupled with both the plurality of switches and the data input. The logic circuit controls the switches to be in one of a DAC mode or a mixer mode. The DAC mode causes the switches to convert the input digital data signal into a DAC analog signal having about the data frequency. The mixer mode, however, causes the switches to convert the input digital data signal into a mixed analog signal having a mixer frequency that is higher than the data frequency.

1. An electronic chip comprising:
 a data input for receiving a digital data signal having a data frequency; 
 a plurality of switches; and 
 a logic circuit operatively coupled with the plurality of switches and the data input, the logic circuit controlling the switches to be in one of a DAC mode or a mixer mode, 
 DAC mode causing the switches to convert the digital data signal into a DAC analog signal having about the data frequency, 
 the mixer mode causing the switches to convert the data signal into a mixer analog signal having a mixer frequency that is higher than the data frequency. 
 
   
   
     2. The chip as defined by  claim 1  further comprising a clock input for receiving a clock signal having a clock frequency, the frequency of the mixer analog signal being a function of the clock frequency. 
   
   
     3. The chip as defined by  claim 2  wherein the mixer frequency increases when the clock frequency increases, the mixer frequency decreasing when the clock signal decreases. 
   
   
     4. The chip as defined by  claim 1  wherein the data input has an interface for receiving a given number of bits representing the digital data signal, the plurality of switches having a total number of switches, the total number being the product of the given number of bits and four. 
   
   
     5. The chip as defined by  claim 1  wherein the plurality of switches comprises a first pair of switches and a second pair of switches, the first pair coupled to a first switch output node, the second pair coupled to a second switch output node, the logic controlling the pairs to ensure that no more than one of the switches in the two pairs is closed at a single time. 
   
   
     6. The chip as defined by  claim 5  further comprising a clock input for receiving a clock signal having a clock frequency, the logic circuit controlling the two pairs of switches so that no one of their switches is closed for two consecutive half-cycles of the clock signal. 
   
   
     7. The chip as defined by  claim 5  wherein the logic circuit produces four control signals, each of the switches in the two pairs of switches receiving one of the four control signals, the logic circuit forwarding a given one of the four control signals to one of the switches when in the DAC mode, the logic circuit forwarding the given control signal to another of the switches when in the mixer mode. 
   
   
     8. The chip as defined by  claim 7  wherein the logic circuit forwards the given control signal to one of the switches in the first pair when in the DAC mode, the logic forwarding the given control signal to one of the switches in the second pair when in the mixer mode. 
   
   
     9. The chip as defined by  claim 1  further comprising means for processing both real and imaginary data to implement a quadrature mixer. 
   
   
     10. A mixer chip comprising:
 a data input for receiving a digital data signal having a data frequency; 
 a first pair of switches; 
 a second pair of switches; 
 a differential output having a first node and a second node, the first pair of switches being coupled with the first node, the second pair of switches being coupled with the second node; and 
 a logic circuit using a clock signal with a clock frequency, the logic circuit causing the first pair and second pair to alternatively produce a signal on their respective nodes for each half-cycle of the clock signal when in a mixer mode, the differential output producing an analog output signal. 
 
   
   
     11. The mixer chip as defined by  claim 10  wherein the logic circuit controls the two pairs of switches to be in one of a DAC mode or the mixer mode,
 the DAC mode causing the switches to convert the digital data signal into a DAC analog signal having about the data frequency, 
 the mixer mode causing the switches to convert the data signal into a mixer analog signal having a mixer frequency that is higher than the data frequency. 
 
   
   
     12. The mixer chip as defined by  claim 11  wherein the logic circuit produces four control signals, each of the switches in the two pairs of switches receiving one of the four control signals, the logic circuit forwarding a given one of the four control signals to one of the switches when in the DAC mode, the logic circuit forwarding the given control signal to another of the switches when in the mixer mode. 
   
   
     13. The mixer chip as defined by  claim 12  wherein the logic circuit forwards the given control signal to one of the switches in the first pair when in the DAC mode, the logic forwarding the given control signal to one of the switches in the second pair when in the mixer mode. 
   
   
     14. The mixer chip as defined by  claim 11  wherein the analog output signal has a frequency that is about a multiple of the clock signal when in the mixer mode. 
   
   
     15. The mixer chip as defined by  claim 10  wherein the logic circuit controls the two pairs of switches so that no one of their switches is closed for two consecutive half-cycles of the clock signal. 
   
   
     16. A method comprising:
 providing a first pair of switches coupled with a first output node; 
 providing a second pair of switches coupled with a second output node, the two pairs of switches being on a single chip; 
 receiving a clock signal having a clock frequency; 
 receiving a digital data signal having a data frequency, the switches producing an output signal on no more than one of the first and second output nodes; and 
 selecting whether the switches are to be in a mixer mode or a DAC mode, 
 the switches cooperating to convert the digital data signal into an analog data signal having about the data frequency when in the DAC mode, 
 the switches cooperating to switch the output signal between the first and second output nodes every half-cycle of the clock signal when in the mixer mode. 
 
   
   
     17. The method as defined by  claim 16  further comprising using the differential output signal between the first output node and the second output node to produce a final signal. 
   
   
     18. The method as defined by  claim 16  wherein when in the mixer mode, the final signal has a final signal frequency that is a multiple of the clock frequency. 
   
   
     19. The method as defined by  claim 16  wherein the data signal remains substantially constant for each full-cycle of the clock signal. 
   
   
     20. The method as defined by  claim 16  wherein selecting comprises causing a logic circuit to produce a logic signal that causes the switches to be in either the DAC mode or the mixer mode, the logic circuit being on a different chip than that of the switches.