Method of forming a high-k gate dielectric layer

Abstract

A method for manufacturing a semiconductor device. The method comprises forming a dielectric layer. Forming the dielectric layer includes depositing a silicon oxide layer on a semiconductor substrate, nitridating the silicon oxide layer to form a nitrided silicon oxide layer and incorporating lanthanide atoms into the nitrided silicon oxide layer to form a lanthanide silicon oxynitride layer.

1. A method for manufacturing a semiconductor device, comprising:
 forming a dielectric layer, including:
 forming a silicon oxide layer on a semiconductor substrate; 
 nitriding said silicon oxide layer to form a nitrided silicon oxide layer; and 
 incorporating lanthanide atoms into said nitrided silicon oxide layer to form a lanthanide silicon oxynitride layer; wherein incorporating said lanthanide atoms includes implanting lanthanide atoms into said nitrided silicon oxide layer and then thermally annealing said lanthanide-implanted nitrided silicon oxide layer. 
 
 
   
   
     2. The method of  claim 1 , wherein a nitrogen content of said lanthanide silicon oxynitride layer ranges from about 6 to 20 atomic percent. 
   
   
     3. The method of  claim 1 , wherein implanting said lanthanide atoms is performed after depositing a polysilicon layer on said nitrided silicon oxide layer. 
   
   
     4. The method of  claim 1 , wherein implanting said lanthanide atoms includes an implantation energy of about 20 to 40 keV, and said lanthanide atom dose ranges from about 5E14 to 5E15 atom/cm 2 . 
   
   
     5. The method of  claim 1 , wherein said implanting is performed after masking regions of said substrate that comprise pMOS transistor regions, such that said lanthanide atoms are implanted selectively into said gate dielectric layers located in nMOS transistor regions of said device. 
   
   
     6. The method of  claim 1 , further comprising forming a polysilicon layer on said nitrided silicon oxide layer prior to said implanting said lanthanide atoms. 
   
   
     7. The method of  claim 1 , wherein incorporating lanthanide atoms includes incorporating ytterbium, gadolinium or dysprosium into said nitrided silicon oxide layer. 
   
   
     8. The method of  claim 1 , wherein said substrate is a silicon substrate; and
 forming said silicon oxide layer includes oxidation of a surface of said silicon substrate. 
 
   
   
     9. The method of  claim 8 , wherein nitriding said silicon oxide layer includes exposing said silicon oxide layer to a remote or decoupled nitrogen plasma to implant said silicon oxide layer to provide an about 6 to 20 atomic percent concentration of nitrogen atoms in said nitrided silicon oxide layer. 
   
   
     10. The method of  claim 8 , wherein nitriding said silicon oxide layer includes NH 3  thermal nitriding. 
   
   
     11. The method of  claim 8 , wherein nitriding said silicon oxide layer includes a thermal anneal step conducted at about 1000° C. for about 60 seconds in an N 2  atmosphere. 
   
   
     12. A method for manufacturing a semiconductor device, comprising forming a transistor including:
 forming a transistor gate dielectric layer, including:
 forming a silicon oxide layer on a semiconductor substrate; 
 nitriding said silicon oxide layer to form a nitrided silicon oxide layer; and 
 implanting lanthanide atoms into said nitrided silicon oxide layer and thermally annealing said lanthanide-implanted nitrided silicon oxide layer to form a lanthanide silicon oxynitride layer; 
 
 forming a transistor gate electrode layer on said nitrided silicon oxide layer; and 
 patterning said gate electrode layer and said nitrided silicon oxide layer. 
 
   
   
     13. The method of  claim 12 , wherein implanting said lanthanide atoms includes an implantation energy of about 20 to 40 keV, and said lanthanide atom dose ranges from about 5E14 to 5E15 atoms/cm 2 . 
   
   
     14. The method of  claim 12 , wherein said gate electrode layer is formed prior to implanting said lanthanide atoms into said nitrided silicon oxide layer. 
   
   
     15. The method of  claim 14 , wherein said patterning is done prior to implanting said lanthanide atoms into said nitrided silicon oxide layer. 
   
   
     16. The method of  claim 14 , wherein said gate electrode layer is a layer of polysilicon. 
   
   
     17. The method of  claim 16 , wherein said layer of polysilicon is about 70 to 90 nm thick; and implanting lanthanide atoms comprises implanting lanthanide atoms at an implantation energy of about 20 to 40 keV, and a dose of about 5E14 to 5E15 atoms/cm 2 . 
   
   
     18. The method of  claim 17 , wherein said layer of polysilicon is about 80 nm thick; and implanting lanthanide atoms comprises implanting ytterbium atoms at an implantation energy of about 35 keV and a dose of about 3E15 to 5E15 atoms/cm 2 . 
   
   
     19. The method of  claim 12 , wherein said semiconductor device comprises nMOS and pMOS transistors; said substrate includes an nMOS transistor region and a pMOS transistor region; forming said transistor comprises forming said nMOS transistor; and said implanting is performed after masking said pMOS transistor region. 
   
   
     20. The method of  claim 12 , further comprising implanting hafnium atoms into said nitrided silicon oxide layer. 
   
   
     21. The method of  claim 20 , wherein said gate electrode layer is an about 80 nm thick layer of polysilicon; and implanting said hafnium atoms comprises implanting hafnium atoms at an implantation energy of about 20 to 40 keV, and a dose of about 5E14 to 5E15 atoms/cm 2 . 
   
   
     22. The method of  claim 12 , wherein thermally annealing said lanthanide-implanted nitrided silicon oxide layer comprises a spike anneal. 
   
   
     23. The method of  claim 12 , wherein thermally annealing said lanthanide-implanted nitrided silicon oxide layer comprises heating from 1000 to 1100° C. for about 0.5 to 5 seconds.