Level shift circuit

Abstract

A level shift circuit prevents a through current in an output circuit connected to a high-voltage power supply, thereby reducing power consumption and noise and enabling a high-speed operation. The level shift circuit includes first and second bias generating circuits that supply a gate bias voltage to each of a PMOS transistor as a first transistor and a NMOS transistor as a second transistor. Each of the first and second bias voltage generating circuits includes a series connection of a diode-connected PMOS transistor and a diode-connected NMOS transistor. The discharge of a capacitor to the high-voltage power supply is prevented, and a through current is prevented when an output signal transitions from a high-level to a low-level and vice versa, whereby power consumption and noise can be reduced.

1. A level shift circuit for producing a high voltage amplitude output signal from a low voltage amplitude input signal, the circuit comprising:
 complementary-type first and second transistors that are connected in series between a high-voltage power supply and a ground potential; 
 a capacitor connected between control electrodes of the first and second transistors; 
 a first bias generating circuit connected to the high-voltage power supply and the control electrode of the first transistor, the first bias generating circuit being configured to apply a first bias voltage to the control electrode of the first transistor; 
 a second bias generating circuit connected to the ground potential and the control electrode of the second transistor, the second bias generating circuit being configured to apply a second bias voltage to the control electrode of the second transistor; 
 a first switch unit configured to turn on or off depending on the low voltage amplitude input signal in order to supply power to the first bias generating circuit while the output signal is at a high-level and to stop the supply of power to the first bias generating circuit while the output signal is at a low-level; and 
 a second switch unit configured to turn on or off depending on the low voltage amplitude input signal in order to stop a supply of power to the second bias generating circuit while the output signal is at the high-level, and to supply power to the second bias generating circuit while the output signal is at the low-level, 
 wherein the high voltage amplitude output signal is outputted from a connecting node of the first and second transistors, 
 wherein the first bias generating circuit includes a first voltage limiting circuit connected between the high-voltage power supply and the control electrode of the first transistor, and a first bias current generating circuit configured to supply a first bias current to the first voltage limiting circuit, wherein the first voltage limiting circuit includes a series connection of a diode-connected transistor having the same characteristics as those of the first transistor and a diode-connected transistor having the same characteristics as those of the second transistor, and 
 wherein the second bias generating circuit includes a second voltage limiting circuit connected between the control electrode of the second transistor and the ground potential, and a second bias current generating circuit configured to supply a second bias current to the second voltage limiting circuit, wherein the second voltage limiting circuit includes a series connection of a diode-connected transistor having the same characteristics as those of the first transistor and a diode-connected transistor having the same characteristic as those of the second transistor. 
 
     
     
       2. The level shift circuit according to  claim 1 , wherein the first and second bias voltages are the same and are either equal to a sum of threshold voltages of the first transistor and the second transistor or smaller than the sum by a predetermined value. 
     
     
       3. The level shift circuit according to  claim 1 , wherein a threshold voltage of at least one of the transistor having the same conductivity type as the first transistor and the transistor having the same conductivity type as the second transistor in each of the first and second voltage limiting circuits is lower than the threshold voltage of the first transistor or the second transistor of the corresponding conductivity type. 
     
     
       4. The level shift circuit according to  claim 1 , wherein the first bias current generating circuit includes a first current limiting unit of which one end is connected to the control electrode of the first transistor, and the first switch unit connected between the other end of the first current limiting unit and the ground potential. 
     
     
       5. The level shift circuit according to  claim 4 , wherein the first current limiting unit includes a resistor or a constant current source. 
     
     
       6. The level shift circuit according to  claim 1 , wherein the second bias current generating circuit includes a second current limiting unit of which one end is connected to the control electrode of the second transistor and of which the other end is connected to the high-voltage power supply or a power supply whose voltage is lower than that of the high-voltage power supply. 
     
     
       7. The level shift circuit according to  claim 6 , further comprising a third switch unit connected between the other end of the second current limiting unit and the power supply whose voltage is lower than that of the high-voltage power supply, wherein the third switch unit is turned on or off depending on the low voltage amplitude input signal. 
     
     
       8. The level shift circuit according to  claim 7 , wherein the third switch unit turns off while the output signal is at the high-level and turns on while the output signal is at the low-level. 
     
     
       9. The level shift circuit according to  claim 6 , wherein the second current limiting unit includes a resistor or a constant current source. 
     
     
       10. The level shift circuit according to  claim 1 , wherein the second switch unit is connected between the control electrode of the second transistor and the ground potential. 
     
     
       11. The level shift circuit according to  claim 1 , wherein the first switch unit turns on while the output signal is at the high-level and turns off while the output signal is at the low-level. 
     
     
       12. The level shift circuit according to  claim 1 , wherein the second switch unit turns on while the output signal is at the high-level and turns off while the output signal is at the low-level. 
     
     
       13. A level shift circuit for producing a high voltage amplitude output signal from a low voltage amplitude input signal, the circuit comprising:
 complementary-type first and second transistors that are connected in series between a high-voltage power supply and a ground potential; 
 a capacitor connected between control electrodes of the first and second transistors; 
 a first bias generating circuit connected to the high-voltage power supply and the control electrode of the first transistor, the first bias generating circuit being configured to apply a first bias voltage to the control electrode of the first transistor; 
 a second bias generating circuit connected to the ground potential and the control electrode of the second transistor, the second bias generating circuit being configured to apply a second bias voltage to the control electrode of the second transistor; 
 a first switch unit configured to turn on or off depending on the low voltage amplitude input signal in order to supply power to the first bias generating circuit while the output signal is at a high-level and to stop the supply of power to the first bias generating circuit while the output signal is at a low-level; and 
 a second switch unit configured to turn on or off depending on the low voltage amplitude input signal in order to stop a supply of power to the second bias generating circuit while the output signal is at the high-level, and to supply power to the second bias generating circuit while the output signal is at the low-level, 
 wherein the high voltage amplitude output signal is outputted from a connecting node of the first and second transistors, 
 wherein each of the first switch unit and the second switch unit includes a transistor having the same characteristics as those of the second transistor, wherein the low voltage amplitude input signal of the same phase is applied to a control electrode of each of the first switch unit and the second switch unit, and wherein the first switch unit is configured to turn off first when the first switch unit and the second switch unit transition from an on-state to an off-state depending on the input signal. 
 
     
     
       14. A level shift circuit for producing a high voltage amplitude output signal from a low voltage amplitude input signal, the circuit comprising:
 complementary-type first and second transistors that are connected in series between a high-voltage power supply and a ground potential; 
 a capacitor connected between control electrodes of the first and second transistors; 
 a first bias generating circuit connected to the high-voltage power supply and the control electrode of the first transistor, the first bias generating circuit being configured to apply a first bias voltage to the control electrode of the first transistor; 
 a second bias generating circuit connected to the ground potential and the control electrode of the second transistor, the second bias generating circuit being configured to apply a second bias voltage to the control electrode of the second transistor; 
 a first switch unit configured to turn on or off depending on the low voltage amplitude input signal in order to supply power to the first bias generating circuit while the output signal is at a high-level and to stop the supply of power to the first bias generating circuit while the output signal is at a low-level; 
 a second switch unit configured to turn on or off depending on the low voltage amplitude input signal in order to stop a supply of power to the second bias generating circuit while the output signal is at the high-level, and to supply power to the second bias generating circuit while the output signal is at the low-level, wherein the high voltage amplitude output signal is outputted from a connecting node of the first and second transistors; and 
 a third bias generating circuit connected between the first switch unit and the ground potential and configured to produce a third bias voltage. 
 
     
     
       15. The level shift circuit according to  claim 14 , wherein the third bias generating circuit includes a series connection of one or more diode-connected transistors. 
     
     
       16. The level shift circuit according to  claim 14 , wherein the third bias generating circuit includes a resistor.