Method of fabricating a trench DMOS (double diffused MOS) transistor

Abstract

Disclosed is a method of fabricating a semiconductor device. The method can include forming a gate material layer on an inner surface of a trench which extends into a part of a semiconductor substrate by passing through an insulating layer formed on the semiconductor substrate, etching the gate material layer to an initial height in the trench above a top surface of the semiconductor substrate, etching the insulating layer such that the thickness of the insulating layer is reduced, forming a gate electrode in the trench by secondarily etching the etched gate material layer, and removing the insulating layer having the reduced thickness.

1. A method of fabricating a semiconductor device comprising the following sequential steps:
 providing a semiconductor substrate; 
 forming an insulating layer on the semiconductor substrate; 
 forming a trench through the insulating layer and a portion of the semiconductor substrate; 
 forming a gate insulating layer on the inner surface of the trench; 
 forming a gate material layer on the insulating layer and in the trench on the gate insulating layer; 
 performing an initial etch of the gate material layer; 
 performing an initial etch of the insulating layer; 
 forming a gate electrode in the trench by performing a second etching process with respect to the initially etched gate material layer; and 
 performing a second etch to the initially etched insulating layer. 
 
     
     
       2. The method according to  claim 1 , wherein providing the semiconductor substrate comprises:
 providing an N type epitaxial layer on an n+ type drain region; and 
 forming a P type body region on the N type epitaxial layer. 
 
     
     
       3. The method according to  claim 2 , wherein forming the trench through the insulating layer and the portion of the semiconductor substrate comprises forming the trench through the P type body region and a portion of the N-type epitaxial layer. 
     
     
       4. The method according to  claim 1 , wherein performing the initial etch of the gate material layer comprises:
 forming a mask layer on the gate material layer; and 
 etching the gate material layer by using the mask layer as an etch mask. 
 
     
     
       5. The method according to  claim 4 , wherein, forming the gate electrode comprises performing the second etching process using the mask layer as the etch mask. 
     
     
       6. The method according to  claim 4 , wherein the mask layer includes material identical to material of the insulating layer. 
     
     
       7. The method according to  claim 6 , wherein the mask layer is formed to have the same thickness as the insulating layer. 
     
     
       8. The method according to  claim 4 , wherein during the performing of the initial etch of the insulating layer, the mask layer is initially etched; and wherein during the performing of the second etch to the initially etched insulating layer, the initially etched mask layer is etched. 
     
     
       9. The method according to  claim 4 , wherein the etch mask provides a pattern for a ground pad, wherein performing the initial etch of the gate material layer forms the ground pad on the insulating layer. 
     
     
       10. The method according to  claim 1 , wherein performing the initial etch of the gate material layer comprises etching the gate material layer to expose an upper surface of the insulating layer, wherein the top surface of the gate material layer remaining in the trench is above the top surface of the semiconductor substrate. 
     
     
       11. The method according to  claim 1 , wherein the insulating layer has a thickness of about 1000 Å to about 1500 Å after performing the initial etch of the insulating layer. 
     
     
       12. The method according to  claim 1 , wherein performing the initial etch of the insulating layer reduces the thickness of the insulating layer, and wherein performing the second etch to the initially etched insulating layer comprises removing the insulating layer having the reduced thickness. 
     
     
       13. The method according to  claim 1 , further comprising forming a source region at a side of the trench. 
     
     
       14. A method of fabricating a semiconductor device, comprising:
 providing a semiconductor substrate; 
 forming an insulating layer on the semiconductor substrate; 
 forming a trench through the insulating layer and a portion of the semiconductor substrate; 
 forming a gate insulating layer on the inner surface of the trench; 
 forming a gate material layer on the insulating layer and in the trench on the gate insulating layer; 
 forming a ground pad on the insulating layer by performing an initial etch of the gate material layer; 
 forming a ground pad on the insulating layer by performing an initial etch of the gate material layer; performing an initial etch of the insulating layer after forming the ground pad; forming a gate electrode in the trench by performing a second etch of the initially etched gate material layer; and performing a second etch to the initially etched insulating layer after forming the gate electrode. 
 
     
     
       15. The method according to  claim 14 , wherein after forming the gate electrode, a top surface of the gate insulating layer is disposed above a top surface of the gate electrode. 
     
     
       16. The method according to  claim 14 , further comprising forming a source region at sides of the trench. 
     
     
       17. The method according to  claim 1 , wherein an upper surface of the initially etched gate material layer is positioned below an upper surface of the insulating layer and above an upper surface of the semiconductor substrate. 
     
     
       18. The method according to  claim 14 , wherein an upper surface of the initially etched gate material layer is positioned below an upper surface of the insulating layer and above an upper surface of the semiconductor substrate.