Transistor of organic light-emitting, method for fabricating the transistor, and organic light-emitting device including the transistor

Abstract

A driving TFT for an organic light-emitting display device includes a gate electrode on a portion of a substrate, a gate insulation layer on an entire surface of the substrate including the ate electrode, a semiconductor layer on the gate insulation layer and covering the gate electrode, the semiconductor layer including an n-type impurity layer, and source and drain electrodes overlapping portions of the semiconductor layer at respective sides thereof.

1. A TFT for an organic light-emitting display device comprising:
 a gate electrode on a substrate; 
 a gate insulation layer on the substrate including the gate electrode; 
 a semiconductor layer on the gate insulation layer, wherein the semiconductor layer includes at least an n-type impurity layer covering the gate electrode entirely; and 
 source and drain electrodes overlapping portions of the semiconductor layer at respective sides thereof. 
 
     
     
       2. The TFT of  claim 1 , wherein the n-type impurity layer includes an amorphous silicon doped with n-type impurity ions at a density of 100 ppm to 10000 ppm. 
     
     
       3. The TFT of  claim 1 , wherein the gate electrode of the driving TFT is connected to a negative driving voltage. 
     
     
       4. The TFT of  claim 1 , wherein the n-type impurity layer is formed at a thickness of 100 Å to 500 Å. 
     
     
       5. The TFT of  claim 1 , further comprising a first amorphous silicon layer and an n+-type impurity layer on the n-type impurity layer. 
     
     
       6. The TFT of  claim 5 , wherein the n+-type impurity layer is formed under the source and drain electrodes to exclude a region therebetween. 
     
     
       7. The TFT of  claim 5 , wherein the first amorphous silicon layer has a thickness of about 1000 Å to about 3000 Å, and the n+-type impurity layer has a thickness of about 100 Å to about 1000 Å. 
     
     
       8. The TFT of  claim 5 , further comprising a second amorphous silicon layer under the n-type impurity layer. 
     
     
       9. The TFT of  claim 8 , wherein the first amorphous silicon layer has a thickness of about 500 Å to about 1500 Å, the second amorphous silicon layer has a thickness of about 100 Å to about 600 Å, and the n+-type impurity layer has a thickness of about 100 Å to about 1000 Å.