Memory cell with buried digit line

Abstract

A memory cell, array and device include an active area formed in a substrate with a vertical transistor including a first end disposed over a first portion of the active area. The vertical transistor is formed as an epitaxial post on the substrate surfaces extends from the surface of the substrate, and includes a gate formed around a perimeter of the epitaxial post. A capacitor is formed on the vertical transistor and a buried digit line vertically couples to a second portion of the active area. An electronic system and method for forming a memory cell are also disclosed.

1. A DRAM cell formed on a surface of a semiconductor substrate, comprising:
 a vertical access transistor including a first end; 
 a capacitor vertically extending from and electrically coupled to a second end of the vertical access transistor; a buried digit line electrically coupled to the first end of the vertical access transistor; and 
 an active area operably coupling the first end of the vertical access transistor and the buried digit line. 
 
     
     
       2. The DRAM cell of  claim 1 , further comprising a vertically oriented contact for electrically coupling the buried digit line to the first end of the vertical access transistor. 
     
     
       3. The DRAM cell of  claim 2 , wherein the vertically oriented contact is non-orthogonal to the semiconductor substrate. 
     
     
       4. The DRAM cell of  claim 1  wherein the active area and the buried digit line at least partially overlap in a plane perpendicular to the semiconductor substrate. 
     
     
       5. The DRAM cell of  claim 4 , wherein the active area is a discrete active area isolated from other discrete active areas. 
     
     
       6. The DRAM cell of  claim 5 , wherein the discrete active area is oriented in a non-orthogonal orientation with the buried digit line. 
     
     
       7. The DRAM cell of  claim 6 , wherein a portion of the discrete active area corresponds to an intersection of the buried digit line and the discrete active area. 
     
     
       8. The DRAM cell of  claim 4 , wherein:
 the active area is configured in a continuous serpentine arrangement around the DRAM cell; and 
 the buried digit line is configured in a continuous serpentine arrangement at least partially overlapping the active area. 
 
     
     
       9. The DRAM cell of  claim 8 , wherein the buried digit line is configured in a serpentine arrangement mirroring the serpentine arrangement of the active area. 
     
     
       10. The DRAM cell of  claim 9 , wherein the serpentine arrangement of the buried digit line and the serpentine arrangement of the active area form a half-weave overlapping arrangement. 
     
     
       11. The DRAM cell of  claim 9 , wherein the serpentine arrangement of the buried digit line and the serpentine arrangement of the active area form a quarter-weave overlapping arrangement. 
     
     
       12. The DRAM cell of  claim 9 , wherein the serpentine arrangement of the buried digit line and the serpentine arrangement of the active area form a subquarter-weave overlapping arrangement. 
     
     
       13. A DRAM cell, comprising:
 a capacitor formed on a first end of a vertical access transistor; 
 a buried digit line electrically coupled to a second end of the vertical access transistor; and 
 an active area for electrically coupling the second end of the vertical access transistor to a contact of the buried digit line. 
 
     
     
       14. The DRAM cell of  claim 2 , wherein the vertically oriented contact is orthogonal to the semiconductor substrate. 
     
     
       15. The DRAM cell of  claim 13 , wherein the contact of the buried digit includes a substantially vertical contact between the buried digit line and the active area. 
     
     
       16. The DRAM cell of  claim 15 , wherein the DRAM cell is formed on a surface of a semiconductor substrate and the active area and the buried digit line at least partially overlap in a plane perpendicular to the semiconductor substrate. 
     
     
       17. The DRAM cell of  claim 16 , wherein the active area is isolated from other active areas. 
     
     
       18. The DRAM cell of  claim 17 , wherein the active area is shared with at least one other DRAM cell. 
     
     
       19. The DRAM cell of  claim 15  wherein:
 the active area is configured in a serpentine arrangement around the DRAM cell; and 
 the buried digit line is configured in a serpentine arrangement at least partially overlapping the active area. 
 
     
     
       20. The DRAM cell of  claim 13 , wherein the buried digit line further includes a substantially sloped contact between the buried digit line and the active area.