A/D converter

Abstract

In an A/D converter, three capacitors are connected to a comparator. The A/D converter also includes three switching circuits that each input a first reference voltage, a second reference voltage, and a third reference voltage in the three capacitors. A control circuit selects at least two of the three switching circuits during a charging period of stray capacitance of each of the capacitors. The control circuit turns on one of the switching devices in the selected switching circuits simultaneously, and during a comparing period by the comparator, selects one of the three capacitors for each comparison, and selects another capacitor in the next comparison.

1. An analog-to-digital converter comprising:
 a first capacitor, a second capacitor, and a third capacitor each configured to sample an analog input voltage in cooperation with a first switching circuit, a second switching circuit, and a third switching circuit, respectively; 
 a reference voltage generator configured to generate a first reference voltage, a second reference voltage, and a third reference voltage for the first capacitor, the second capacitor, and the third capacitor, respectively, and to apply the first reference voltage, the second reference voltage, and the third reference voltage to first terminals of the first capacitor, the second capacitor, and the third capacitor, respectively; 
 a comparator between the analog input voltage and the first reference voltage, the second reference voltage, and the third reference voltage configured to compare a voltage at second terminals of the first capacitor, the second capacitor, and the third capacitor with a predetermined value; 
 a charging timing controller configured to control the reference voltage generator to apply two reference voltages in order to obtain an analog-to-digital converted value at an (N+1)th most significant bit to the first terminal of two of the first capacitor, the second capacitor, and the third capacitor before an analog-to-digital converted value at an Nth most significant bit is determined, where N is an integer that is larger than or equal to one; and 
 a comparing timing controller configured to control the comparator to determine an analog-to-digital converted value at the (N+1)th most significant bit by controlling the comparator to compare a voltage at the second terminals of the first capacitor, the second capacitor, and the third capacitor with the first terminal applied with a reference voltage according to the analog-to-digital converted value at the Nth most significant bit with a predetermined value after the analog-to-digital converted value at the Nth most significant bit is determined. 
 
     
     
       2. The analog-to-digital converter of  claim 1 , wherein the comparing timing controller is configured to control the comparator to compare a voltage at the second terminal of one of the first, second and third capacitors which is not applied the two reference voltages with a predetermined value, in order to calculate the analog-to-digital converted value at the Nth most significant bit, while the two reference voltages for obtaining the analog-to-digital converted value at the (N+1)th most significant bit are applied to the first terminal of two of the first capacitor, the second capacitor, and the third capacitor. 
     
     
       3. The analog-to-digital converter of  claim 1 , wherein the charging timing controller is configured to control the reference voltage generator to apply a reference voltage in order to obtain the analog-to-digital converted value at the Nth most significant bit to the first terminal of one of the first capacitor, the second capacitor, and the third capacitor, and simultaneously to apply two reference voltages in order to obtain the analog-to-digital converted value at the (N+1)th most significant bit to the first terminal of two capacitors not applied the reference voltage, and
 the comparing timing controller is configured to control the comparator to compare a voltage at the second terminal of the capacitor controlled by the comparing timing controller with the first terminal of the capacitor applied with the reference voltage in order to obtain the analog-to-digital converted value at the Nth most significant bit, with a predetermined value, to calculate the analog-to-digital converted value at the Nth most significant bit, to compare a voltage at the second terminal of one of the first capacitor, the second capacitor, and the third capacitor with the first terminal is applied with the reference voltage according to the analog-to-digital converted value at the Nth most significant bit with a predetermined value, and to determine the analog-to-digital converted value at the (N+1)th most significant bit. 
 
     
     
       4. The analog-to-digital converter of  claim 1 , wherein the reference voltage generator comprises:
 a series resistor configured to generate a number of n th power of two pieces of divided voltages by dividing a standard voltage where n is a bit width of analog-to-digital conversion; and 
 a switch configured to input the divided voltages generated by the series resistor to the first terminals of the first capacitor, the second capacitor, and the third capacitor as the first reference voltage, the second reference voltage, and the third reference voltage, respectively. 
 
     
     
       5. The analog-to-digital converter of  claim 1 , wherein the reference voltage generator comprises:
 n pieces of resistors connected in parallel to a standard voltage where n is a bit width of analog-to-digital conversion; 
 n pieces of switching circuits connected in series to the n pieces of the resistors; and 
 an operational amplifier connected to the resistors via the switching circuits. 
 
     
     
       6. The analog-to-digital converter of  claim 1 , wherein the comparator comprises:
 a selecting circuit configured to select at least one of voltages at the second terminals of the first capacitor, the second capacitor, and the third capacitor, and to cause the comparator to compare the voltage with a predetermined value; 
 an operational amplifier configured to compare the voltage selected by the selecting circuit with the predetermined value, and to output a result of comparison as an analog-to-digital converted value at the Nth most significant bit; and 
 a fourth switching circuit configured to connect the second terminals of the first capacitor, second capacitor, and third capacitor to a predetermined potential while the analog input voltage is sampled via the first terminals of the first capacitor, the second capacitor, and the third capacitor. 
 
     
     
       7. The analog-to-digital converter of  claim 6 , wherein the fourth switching circuit is configured to connect the second terminals of the first capacitor, the second capacitor, and the third capacitor to a ground potential while the analog input voltage is sampled via the first terminals of the first capacitor, the second capacitor, and the third capacitor. 
     
     
       8. The analog-to-digital converter of  claim 6 , wherein the fourth switching circuit is configured to connect the second terminals of the first capacitor, the second capacitor, and the third capacitor to an output terminal of the operational amplifier while the analog input voltage is sampled via the first terminals of the first capacitor, the second capacitor, and the third capacitor. 
     
     
       9. The analog-to-digital converter of  claim 1 , wherein the comparator comprises:
 a first field effect transistor, a second field effect transistor, and a third field effect transistor whose gates are connected to the second terminal of the first capacitor, the second capacitor, and the third capacitor, respectively; 
 a fourth switching circuit configured to select at least one of drains of the first field effect transistor, the second field effect transistor, and the third field effect transistor; 
 a fourth field effect transistor configured to output a difference between an electric current flowing in the drain selected by the fourth switching circuit with an electric current flowing in a drain of the fourth field effect transistor; and 
 a fifth switching circuit configured to connect the second terminals of the first capacitor, the second capacitor, and the third capacitor to a predetermined potential while the analog input voltage is sampled via the first terminals of the first capacitor, the second capacitor, and the third capacitor. 
 
     
     
       10. The analog-to-digital converter of  claim 1 , further comprising a successive approximation register configured to hold an output from the comparator. 
     
     
       11. An analog-to-digital converter comprising:
 a first capacitor, a second capacitor, and a third capacitor each configured to sample an analog input voltage in cooperation with a first switching circuit, a second switching circuit, and a third switching circuit, respectively; 
 a fourth switching circuit configured to connect the first capacitor and the second capacitor with each other; 
 a fifth switching circuit configured to connect the second capacitor and the third capacitor with each other; 
 a reference voltage generator configured to generate a first reference voltage, a second reference voltage, and a third reference voltage for the first capacitor, the second capacitor, and the third capacitor, respectively, to apply the first reference voltage, the second reference voltage, and the third reference voltage to first terminals of the first capacitor, the second capacitor, and the third capacitor, respectively; 
 a comparator between the analog input voltage and the first reference voltage, the second reference voltage, and the third reference voltage configured to compare a voltage at second terminals of the first capacitor, the second capacitor, and the third capacitor with a predetermined value; 
 a more significant bit conversion controller configured to control the reference voltage generation circuit to apply two reference voltages for obtaining the analog-to-digital converted value at the (N+1)th most significant bit to the first terminals of two of the first capacitor, the second capacitor, and the third capacitor, and to control the comparator to determine the analog-to-digital converted value at the (N+1)th most significant bit by controlling the comparator to compare a voltage at second terminals of the first capacitor, the second capacitor, and the third capacitor with the first terminal applied with the reference voltage according to the analog-to-digital converted value at the Nth most significant bit with a predetermined value, after the analog-to-digital converted value at the Nth most significant bit is determined, for Mth most significant bits, before the analog-to-digital converted value at Nth most significant bit is determined with the fourth and the fifth switching circuits turned off, where M and N are natural numbers and M is equal to or larger than N; and 
 a less significant bit conversion controller configured to controls the reference voltage generation circuit to apply a reference voltage for obtaining the analog-to-digital converted value at a Kth most significant bit to the first terminal of the first capacitor, the second capacitor, and the third capacitor where K is an integer larger than or equal to (M+l), with the first terminal of the first capacitor, the second capacitor, and the third capacitor connected with each other by turning on the fourth switching circuit and the fifth switching circuit, and to control the comparator to determine the analog-to-digital converted value at the Kth most significant bit by controlling the comparator to compare a voltage at the another terminal of each of the first capacitor, the second capacitor, and the third capacitor with the first terminal applied with the reference voltage with a predetermined value, for the (M+1)th most significant bit or the bits less significant. 
 
     
     
       12. The analog-to-digital converter of  claim 11 , wherein the more significant bit conversion controller is configured to control the comparator to compare a voltage at the second terminal of one of the first capacitor, the second capacitor, and the third capacitor which is not applied the two reference voltages with a predetermined value, and to calculate the analog-to-digital converted value at the Nth most significant bit, while the two reference voltages for obtaining the analog-to-digital converted value at the (N+1)th most significant bit are applied to the first terminals of two of the first capacitor, the second capacitor, and the third capacitor. 
     
     
       13. The analog-to-digital converter of  claim 11 , wherein the more significant bit conversion controller is configured to control the reference voltage generator to apply a reference voltage for obtaining the analog-to-digital converted value at the Nth most significant bit to the first terminal of one of the first capacitor, the second capacitor, and the third capacitor, and simultaneously to apply two reference voltages for obtaining the analog-to-digital converted value at the (N+1)th most significant bit to the first terminal of the two capacitors not applied the reference voltage, and to control the comparator to compare a voltage at the second terminal of the capacitor with the terminal applied with the reference voltage for obtaining the analog-to-digital converted value at the Nth most significant bit with a predetermined value, to calculate the analog-to-digital converted value at the Nth most significant bit, and to compare a voltage at the second terminal of one of the first capacitor, the second capacitor, and the third capacitor with the terminal applied with the reference voltage according to the analog-to-digital converted value at the Nth most significant bit with a predetermined value, in order to determine the analog-to-digital converted value at the (N+1)th most significant bit. 
     
     
       14. The analog-to-digital converter of  claim 11 , wherein the reference voltage generator comprises:
 a series resistor configured to generate a number of nth power of two pieces of divided voltages by dividing a standard voltage where n is a bit width of analog-to-digital conversion; and 
 a switch configured to input the divided voltages generated by the series resistor to the first terminals of the first capacitor, the second capacitor, and the third capacitor as the first reference voltage, the second reference voltage, and the third reference voltage, respectively. 
 
     
     
       15. The analog-to-digital converter of  claim 11 , wherein the reference voltage generator comprises:
 n pieces of resistors connected in parallel to a standard voltage where n is a bit width of analog-to-digital conversion; 
 n pieces of switching circuits each connected in series to the n pieces of the resistors; and 
 an operational amplifier connected to the resistors via the switching circuits. 
 
     
     
       16. The analog-to-digital converter of  claim 11 , wherein the comparator comprises:
 a selecting circuit configured to select at least one of voltages at the second terminals of the first capacitor, the second capacitor, and the third capacitor, and to cause the comparator to compare the voltage with a predetermined value; 
 an operational amplifier configured to compare the voltage selected by the selecting circuit with the predetermined value, and to output a result of comparison as an analog-to-digital converted value at the Nth. most significant bit; and 
 a fourth switching circuit configured to connect the second terminals of the first capacitor, second capacitor, and third capacitor to a predetermined potential while the analog input voltage is sampled via the first terminals of the first capacitor, the second capacitor, and the third capacitor. 
 
     
     
       17. The analog-to-digital converter of  claim 16 , wherein the sixth switching circuit is configured to connect the second terminals of the first capacitor, the second capacitor, and the third capacitor to a ground potential while the analog input voltage is sampled via the first terminals of the first capacitor, the second capacitor, and the third capacitor. 
     
     
       18. The analog-to-digital converter of  claim 16 , wherein the sixth switching circuit is configured to connect the second terminals of the first capacitor, the second capacitor, and the third capacitor to an output terminal of the operational amplifier while the analog input voltage is sampled via the first terminal of the first capacitor, the second capacitor, and the third capacitor. 
     
     
       19. The analog-to-digital converter of  claim 11 , wherein the comparator comprises:
 a first field effect transistor, a second field effect transistor, and a third field effect transistor whose gates are connected to the second terminal of the first capacitor, the second capacitor, and the third capacitor, respectively; 
 a sixth switching circuit configured to select at least one of drains of the first field effect transistor, the second field effect transistor, and the third field effect transistor; 
 a fourth field effect transistor configured to output a difference between an electric current flowing in the drain selected by the sixth switching circuit with an electric current flowing in a drain of the fourth field effect transistor; and 
 a seventh switching circuit configured to connect the second terminals of the first capacitor, the second capacitor, and the third capacitor to a predetermined potential while the analog input voltage is sampled via the first terminals of the first capacitor, the second capacitor, and the third capacitor. 
 
     
     
       20. An analog-to-digital converter comprising:
 a first capacitor, a second capacitor, and a third capacitor each configured to sample an analog input voltage in cooperation with a first switching circuit, a second switching circuit, and a third switching circuit, respectively; 
 a reference voltage generator configured to generate a first reference voltage, a second reference voltage, and a third reference voltage, for the first capacitor, the second capacitor, and the third capacitor, respectively, and to apply the first reference voltage, the second reference voltage, and the third reference voltage to first terminals of the first capacitor, the second capacitor, and the third capacitor, respectively; 
 a comparator between the analog input voltage and the first reference voltage, the second reference voltage, and the third reference voltage configured to compare a voltage at second terminals of the first capacitor, the second capacitor, and the third capacitor with a predetermined value; and 
 a control circuit configured to control charge timings either during a previous comparison for a current comparison or while the reference voltages generated by the reference voltage generator are applied to the first capacitor, the second capacitor, and the third capacitor.