Semiconductor device with test pads and pad connection unit

Abstract

A semiconductor device includes at least one first type of pad and at least one second type of pad having a different area from the first type of pad. A pad connection unit electrically couples the at least one second type of pad to an integrated circuit of the semiconductor device during a test mode, and disconnects the at least one second type of pad from the integrated circuit during a normal operating mode.

1. A semiconductor device comprising:
 at least one first type of pad; 
 at least one second type of pad having a different area from the first type of pad; and 
 a pad connection unit for electrically coupling the at least one second type of pad to an integrated circuit of the semiconductor device during a predetermined operating mode that is a test mode, 
 wherein at least one test signal is applied on said at least one second type of pad during said test mode, and wherein no test signal is applied on said at least one first type of pad during said test mode. 
 
     
     
       2. The semiconductor device of  claim 1 , wherein the pad connection unit disconnects the at least one second type of pad from the integrated circuit during an operating mode that is not the predetermined operating mode. 
     
     
       3. The semiconductor device of  claim 2 , wherein the pad connection unit generates a high impedance between the at least one second type of pad and the integrated circuit during the operating mode that is not the predetermined operating mode. 
     
     
       4. The semiconductor device of  claim 1 , wherein the at least one second type of pad has a larger area than an area of the at least one first type of pad such that the first type of pad has a smaller capacitance than the second type of pad. 
     
     
       5. The semiconductor device of  claim 4 , wherein the at least one second type of pad has an area that sufficiently makes electrical contact with a test probe during wafer testing of the semiconductor device. 
     
     
       6. The semiconductor device of  claim 4 , wherein the at least one second type of pad is disposed in a periphery area of the semiconductor device. 
     
     
       7. The semiconductor device of  claim 4 , wherein the at least one first type of pad is disposed in a center area of the semiconductor device. 
     
     
       8. The semiconductor device of  claim 7 , wherein the at least one first type of pad is a bump pad for the semiconductor device formed as part of a flip-chip package. 
     
     
       9. The semiconductor device of  claim 1 , wherein the at least one first type of pad is a bump pad for the semiconductor device formed as part of a flip-chip package. 
     
     
       10. The semiconductor device of  claim 9 , wherein the semiconductor device is a memory device. 
     
     
       11. The semiconductor device of  claim 1 , wherein the pad connection unit includes:
 an output buffer coupled to the at least one second type of pad; and 
 pass-gates controlled by a mode signal to electrically couple the integrated circuit to the at least one second type of pad via the output buffer during the predetermined operating mode. 
 
     
     
       12. The semiconductor device of  claim 11 , wherein the pass-gates are controlled to electrically couple at least one node of the integrated circuit to the at least one second type of pad during the predetermined operating mode. 
     
     
       13. The semiconductor device of  claim 12 , further comprising:
 another output buffer electrically coupled to the at least one node at all times. 
 
     
     
       14. The semiconductor device of  claim 1 , wherein the pad connection unit disconnects the at least one first type of pad from the integrated circuit during the predetermined operating mode. 
     
     
       15. The semiconductor device of  claim 14 , wherein the pad connection unit electrically couples the at least one first type of pad to the integrated circuit for an operating mode that is not the predetermined operating mode. 
     
     
       16. The semiconductor device of  claim 15 , wherein the pad connection unit disconnects the at least one second type of pad from the integrated circuit during the operating mode that is not the predetermined operating mode. 
     
     
       17. The semiconductor device of  claim 16 , wherein the at least one second type of pad has a larger area than an area of the at least one first type of pad such that the first type of pad has a smaller capacitance than the second type of pad. 
     
     
       18. The semiconductor device of  claim 17 , wherein the at least one second type of pad is disposed in a periphery area of the semiconductor device, and wherein the at least one first type of pad is disposed in a center area of the semiconductor device. 
     
     
       19. The semiconductor device of  claim 18 , wherein the at least one first type of pad is a bump pad for the semiconductor device that is a memory device formed as part of a flip-chip package.